关键词: CMOS集成电路, 闩锁效应, 外延片, 穿通击穿

Abstract: Potential parasitic structure in CMOS integrated circuits may cause latch-up effect from time to time.To solve the problem，the paper makes experiments to explore the relationship between well doping concentration and breakdown voltage in CMOS chips with thin epitaxy technique via wafer testing. Aneffective method increasing breakdown voltage of CMOS deviceswhile retaining epitaxy thickness and anti-latch-up capability is proposed.

Key words: CMOS integrated circuit, latch-up effect, epitaxy wafer, punch-through breakdown