中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

导航

电子与封装 ›› 2018, Vol. 18 ›› Issue (8): 28 -32. doi: 10.16257/j.cnki.1681-1070.2018.0088

• 电路设计 • 上一篇    下一篇

一种MCU可测性优化设计

范学仕,刘云晶   

  1. 中科芯集成电路股份有限公司,江苏 无锡 214072
  • 出版日期:2018-08-20 发布日期:2018-08-20
  • 作者简介:范学仕(1991—),男,安徽滁州人,硕士学历,2016年毕业于南京航空航天大学航空宇航推进理论与工程专业,助理工程师,现从事MCU数字设计及低功耗技术研究。

The Optimal Design for Testability on MCU

FAN Xueshi, LIU Yunjing   

  1. China Key System Co, Ltd, Wuxi 214072, China
  • Online:2018-08-20 Published:2018-08-20

摘要: 为了降低测试成本,提高测试效率,将测试资源划分技术和测试端口复用技术相结合,基于ATE外部测试和BIST内部测试的优点,进行可测性设计。基于ATE的外部测试方法,设计了数字逻辑SCAN链和模拟IP测试模式。基于BIST内部测试方法,设计了MBIST电路,对Memory进行测试。为更高效地下载程序和功能验证,设计了支持标准SPI协议的通用测试接口|同时设计了测试模式管理模块,对整个可测性设计进行优化,可实现多个IP同时测试,并在实际芯片中得到验证。

关键词: MCU, 可测性设计, 资源划分技术, MBIST

Abstract: Based on the advantages of ATE external test and MBIST internal test, a DFT design methods combined the test resource partition (TRP) technology and port reuse technology, was presented in this paper for the sake of reducing test cost and improving test efficiency. The SCAN chains of digital logical and test modes of analog IPs were designed based on ATE external test. What’s more, the MBIST circuit for memory testing was devised based on MBIST internal test. Besides, a universal testing interface supporting standard SPI protocol was designed to enhance efficiency of testing and downloading. In order to optimize the whole design, a management module of test modes was proposed, which actualized the testing for multi-IPs at the same time. The proposed DFT has been implemented in an actual wafer.

Key words: MCU, DFT, TRP, MBIST

中图分类号: