关键词: 内存组件, DDR3, 芯片堆叠, 信号完整性, 阻抗

Abstract: Signal integrity analysis and optimization were performed on the packaging and substrate design of a DDR3 die-stacking bonding memory module. The sectional line impedance and delay parameters are scanned on the equivalent circuit model for DDR3 transmission line. The results show that the optimized impedance and delay settings increase the signal eye height and therefore improve the signal quality, which is attributed to the capacitive load compensation. According to the signal eye diagram and the timing analysis results, the design conforms to JEDEC standard.

Key words: memorymodule, DDR3, die-stacking, signalintegrity, impedance