中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

导航

电子与封装

• 电路与系统 •    下一篇

13位高无杂散动态范围的SAR ADC

杨志新,Maureen Willis,高  博,龚  敏   

  1. 四川大学物理学院,成都  610065
  • 收稿日期:2021-12-22 修回日期:2022-03-07 出版日期:2022-03-30 发布日期:2022-03-30
  • 通讯作者: 杨志新

13-bit High Spurious-Free Dynamic Range SAR ADC

YANG Zhixin, WILLIS Maureen, GAO Bo, GONG Min   

  1. School of Physics, Sichuan University, Chengdu 610065, China
  • Received:2021-12-22 Revised:2022-03-07 Online:2022-03-30 Published:2022-03-30

摘要: 基于标准0.18 μm CMOS工艺,设计了一款采样率为500 kS/s的13位逐次逼近型模数转换器(Successive Approximation Analog-to-Digital Converter,SAR ADC)芯片。该转换器内集成了多路复用器、比较器、SAR逻辑电路和数模转换器(Digital-To-Analog Converter,DAC)电容阵列等模块,实现了数字位的串行输出。使用7+6分段式电容阵列及下极板采样和电荷重分配原理,有效降低了ADC整体电容值及功耗。使用两级预放大的比较器和电荷存储技术降低了失调误差,比较器精度为0.3 mV。在2.5 V电源电压和500 kS/s的采样频率下,后仿真结果表明,ADC的无杂散动态范围为97.14 dB,信噪比为78.7 dB,有效位数为12.78 bit。

关键词: SAR ADC, 比较器, 无杂散动态范围, 电荷重分配

Abstract: Based on the standard 0.18 μm CMOS process, a 13-bit successive approximation analog-to-digital converter (SAR ADC) chip with a sampling rate of 500 kS/s is designed. The converter integrates multiplexer, comparator, SAR logic circuit, digital-to-analog converter (DAC) capacitor array and other modules. It has achieved serial digital output. By using 7+6 segmented capacitor array with bottom plate sampling and the principle of charge redistribution, the overall capacitance and power consumption of ADC are effectively reduced. The comparator adopts two stage pre-amplifier, and applies the charge technology to reduce the offset error. So, the comparator has achieved the accuracy of 0.3 mV. The post-simulation under the power supply voltage of 2.5 V and the sampling frequency of 500 kS/s show that the spurious-free dynamic range of ADC is 97.14 dB, the signal-to-noise ratio is 78.7 dB, and the effective number of bits is 12.78 bit.

Key words: SAR ADC, comparator, spurious-free dynamic range, charge redistribution