关键词: SAR ADC, 比较器, 无杂散动态范围, 电荷重分配

Abstract: Based on the standard 0.18 μm CMOS process, a 13-bit successive approximation analog-to-digital converter (SAR ADC) chip with a sampling rate of 500 kS/s is designed. The converter integrates multiplexer, comparator, SAR logic circuit, digital-to-analog converter (DAC) capacitor array and other modules. It has achieved serial digital output. By using 7+6 segmented capacitor array with bottom plate sampling and the principle of charge redistribution, the overall capacitance and power consumption of ADC are effectively reduced. The comparator adopts two stage pre-amplifier, and applies the charge technology to reduce the offset error. So, the comparator has achieved the accuracy of 0.3 mV. The post-simulation under the power supply voltage of 2.5 V and the sampling frequency of 500 kS/s show that the spurious-free dynamic range of ADC is 97.14 dB, the signal-to-noise ratio is 78.7 dB, and the effective number of bits is 12.78 bit.

Key words: SAR ADC, comparator, spurious-free dynamic range, charge redistribution