关键词: RISC-V, 神经网络, 可变张量加速器, 通用矩阵乘, 深度学习编译器

Abstract: To solve the problems of few artificial intelligence (AI) processors based on open reduced instruction set computer-FIVE (RISC-V), unstable supply chain of advanced RISC machine (ARM) architectures and weak autonomy and controllability, the system on chip (SoC) architecture of neural network inference accelerator based on RISC-V processor is designed. SoC architecture is built based on open source free projects. The instruction set of the deep neural network accelerator is designed based on a variable tensor accelerator (VTA) architecture. The processor and VTA are connected by advanced eXtensible interface (AXI), and data are transferred through a shared memory. The convolutional operation and neural network deployment are realized based on a deep learning compiler. Experimental results show that the designed architecture can flexibly realize a variety of mainstream deep neural network reasoning tasks. The number of multiply and accumulate cells (MACs) can reach 1024 and the quantization length is a signed 8-bit integer (INT8). The compiler supports mainstream neural network compilations. The modified ZFNet and ResNet20 neural network image classification demonstrations are completed with overall accuracies of 78.95% and 84.81% on field programmable gate array (FPGA) circuits, respectively.

Key words: RISC-V, neural network, versatile tensor accelerator, general matrix multiplication, deep learning compiler