关键词: 数据采集系统, 采样时间失配, FPGA, 时间交织, 时钟链路

Abstract: With the improvement of communication bandwidth, the requirements of the system for data acquisition bandwidth are gradually increasing. In order to break the performance bottleneck of single channel data acquisition chip, time interleaving technology has attracted more and more attention. An ultra wideband (UWB) data acquisition system based on time interleaving technology is introduced, and the construction principle of the key modules of the data acquisition system is expounded. The 12 GSa/s 12 bit UWB data acquisition system is realized by designing a low-jitter four-phase clock generation module, a micro variable delay limit module and an input signal extraction module. The test results show that the effective number of bits (ENOB) of the data acquisition system under the single tone signal of 10 MHz-2 GHz is not less than 7.2 bit, and the spurious free dynamic range (SFDR) is more than 58 dB. The broadband signal test results show that the signal noise ratio (SNR) reaches 30 dB, which meets the design requirements.

Key words: data acquisition system, timing mismatch, FPGA, time interleaving technology, clock link