关键词: RISC-V, 神经网络, 可变张量加速器, 通用矩阵乘, 深度学习编译器

Abstract: To solve the problem of less artificial intelligence (AI) accelerators based on open reduced instruction set computer-FIVE (RISC-V) instruction set, unstable supply chain of advanced RISC machines (ARM) architecture and weak autonomy and controllability, the system on chip (SoC) architecture of neural network inference accelerator based on RISC-V processor is designed. SoC architecture is built based on open source free project; The instruction set of deep neural network accelerator is designed based on the open source variable tensor accelerator architecture; The processor and versatile tensor accelerator (VTA) are connected by advanced eXtensible interface (AXI) bus protocol, and data transfer between the processor and the VTA through the shared memory; Convolution operation and network deployment are realized through deep learning compiler. The experimental results show that the designed architecture can flexibly realize a variety of mainstream deep neural network reasoning tasks. The number of multiply and accumulate operations (MAC) can reach 1024 and the quantization length is signed 8-bit integer (INT8). The compiler supports mainstream neural network compilation. In addition, the demonstration of M-ZFNet and M-ResNet20 neural network image classification is completed, and the overall accuracy of field programmable gate array (FPGA) is 78.95% and 84.81% respectively.

Key words: RISC-V,  neural network,  versatile tensor accelerator,  general matrix multiplication,  deep learning compiler