关键词: FPGA, U-Net网络, 硬件加速, 卷积运算

Abstract: With the rapid development of deep learning, neural network algorithm is widely used in the field of image processing. Since the hardware computation ability has limited the implementation and application of neural networks, FPGA-based neural network hardware accelerators have been proposed one after another. As a special convolutional neural network, U-Net network is of great significance in biomedical image segmentation. The computation bottleneck of U-Net network is the convolution computation unit. The hardware circuit design methods such as loop unrolling and loop pipelining are used to improve the parallelism of convolution computation hardware accelerator and the overall computation performance of hardware system by consuming FPGA internal hardware resources. Finally, convolution computation hardware accelerator design of the U-Net network was realized on the Pynq-Z1 heterogeneous platform, and the software and hardware system development of the entire U-Net network was completed. The experiment shows that the performance of the U-Net hardware accelerator is 19.690 times of the original, which is an effective neural network acceleration scheme.

Key words: FPGA, U-Net network, hardware acceleration, convolution computation