关键词: 声纳, 波束形成, DSP, FPGA

Abstract: Beamforming is the main technique for detecting targets in sonar detection system. In the existing equipment, DSP is mainly used to realize the beamforming algorithm. In the process of implementing beamforming algorithm with DSP, the sequential execution architecture of DSP itself is considered. If single-chip DSP processing is used, there is a very large time delay between input signal and output result. If five-chip DSP processing is used, the power consumption will increase to five times and the time delay will be 200 ms. By using FPGA and designing parallel operation program structure to realize beamforming algorithm, the time delay and power consumption can be greatly reduced to 1/10 of the results by DSP. The designed beamformer uses 100 MHz clock, which shortens the operation time from 200 ms to about 10 ms, and reduces power consumption to 1/5 of the results by five DSPs.

Key words: sonar, beamforming, DSP, FPGA