[1] 崔义智. 低功耗技术在后端设计中的应用[D]. 上海:复旦大学,2008. [2] 秋攀,乔树山. SoC低功耗多电压设计方法的研究进展[J]. 半导体技术, 2015, 40(3): 167-173,238. [3] 钟杨源,朱宇耀,施隆照. 基于SoC的低功耗管理模块设计[J]. 中国集成电路, 2016, 25(4): 38-42. [4] 莫东杰,熊晓明. 一种低功耗SoC的动态时钟控制技术的应用[J]. 中国集成电路, 2016, 25(6): 19-25, 37. [5] BENINI L, BOGLIOLO A, MICHELI G D. A survey of design techniques for system-level dynamic power management[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000, 8(3): 299-316. [6] YU Z G, WEI J H. Low power design and implementation for a SoC[C]// 2008 9th International Conference on Solid-State and Integrated-Circuit Technology, Beijing, 2008: 2184-2187. [7] REN Z Y, KROGH B H, MARCULESCU R. Hierarchical adaptive dynamic power management[C]// Proceedings Design, Automation and Test in Europe Conference and Exhibition, Paris, 2004: 136-141. [8] MOHANTY S P, RANGANATHAN N, KRISHNA V. Datapath scheduling using dynamic frequency clocking[C]// Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002, Pittsburgh, 2002. [9] 史兴强,范学仕. 一种SoC低功耗模式设计与实现[J]. 电子与封装, 2018, 18(2): 40-45. [10] VO M H. The merged clock gating architecture for low power digital clock application on FPGA[C]// 2018 International Conference on Advanced Technologies for Communications (ATC), Ho Chi Minh City, 2018. [11] 龚号, 王晓蕾, 周敏, 等. 一种用于TDC的低功耗多相时钟生成电路[J]. 微电子学, 2023, 53(5): 846-852. |