关键词: RISC-V, 可重构计算, 非线性计算, 人工智能, SoC

Abstract: A reconfigurable intelligent acceleration core architecture is proposed and a reconfigurable activation function multiply-accumulate unit (ACT-MAC) is designed, aiming at improving the utilization of computing resources under low power constraints. A reconfigurable computing array based on ACT-MAC is designed in the acceleration core, and hardware acceleration of algorithms such as convolution, pooling, long short-term memory (LSTM) and activation function is supported. The acceleration core utilizes a ping-pong pipeline design to optimize memory allocation, significantly enhancing data processing efficiency. This acceleration core is integrated with the open-source RISC-V processor through the nuclei instruction co-unit extension (NICE) interface, forming a complete system on chip (SoC). The design is implemented as a chip prototype on the Nexys Video field programmable gate array (FPGA), on which networks such as LeNet, VGG16, and LSTM are deployed, demonstrating the application potential of this SoC chip prototype in areas such as image classification and semantic recognition. In comparison with recent approaches, this design achieves enhanced digital signal processing (DSP) efficiency while retaining a high energy efficiency ratio, and facilitates hardware acceleration for a multitude of artificial intelligence algorithms, thereby highlighting its broad potential in embedded application scenarios.

Key words: RISC-V, reconfigurable computation, non-linear computation, artificial intelligence, SoC