基于硅通孔互连的芯粒集成技术研究进展

doi:10.16257/j.cnki.1681-1070.2024.0124

摘要/Abstract

摘要： 通过先进封装技术实现具有不同功能、工艺节点的异构芯粒的多功能、高密度、小型化集成是延续摩尔定律的有效方案之一。在各类的先进封装解决方案中，通过硅通孔（TSV）技术实现2.5D/3D封装集成，可以获得诸多性能优势，如极小的产品尺寸、极短的互连路径、极佳的产品性能等。对TSV技术的应用分类进行介绍，总结并分析了目前业内典型的基于TSV互连的先进集成技术，介绍其工艺流程和工艺难点，对该类先进封装技术的发展趋势进行展望。

关键词: 硅通孔, 先进封装, 芯粒, 异构集成, 2.5D封装, 3D封装

Abstract: Multi-functional, high-density and miniaturized integration of heterogeneous Chiplets with different functions and process nodes through advanced packaging technology is one of the effective solutions to continue Moore's law. Among the various types of advanced packaging solutions, 2.5D/3D packaging integration based on through silicon via (TSV) technology has a number of performance advantages, such as extremely small product size, extremely short interconnect paths and excellent product performance. The application classification of TSV technology is introduced. The typical advanced integration technologies based on TSV interconnection in the industry are summarized and analyzed, and their process flow and process difficulties are introduced. The development trend of this type of advanced packaging technology is prospected.

Key words: through silicon via, advanced packaging, Chiplet, heterogeneous integration, 2.5D packaging, 3D packaging

中图分类号:

TN305.94

张爱兵, 李洋, 姚昕, 李轶楠, 梁梦楠. 基于硅通孔互连的芯粒集成技术研究进展[J]. 电子与封装, 2024, 24(6): 060110 .

ZHANG Aibing, LI Yang, YAO Xin, LI Yi’nan, LIANG Mengnan. Research Progress of Chiplet Integration Technology Based on Through Silicon Via Interconnection[J]. Electronics & Packaging, 2024, 24(6): 060110 .

参考文献

[1] CHEN T C. Where CMOS is going: Trendy hype vs. real technology[C]// IEEE International Solid-State Circuits Conference, San Francisco, 2006.
[2] HANCOCK T M, DEMMIN J C. Heterogeneous and 3D integration at DARPA[C]// 2019 International 3D Systems Integration Conference (3DIC), Sendai, 2019: 1-4.
[3] 蒋剑飞, 王琴, 贺光辉, 等. Chiplet技术研究与展望[J]. 微电子学与计算机, 2022, 39(1): 1-6.
[4] 许居衍, 黄安君. 后摩尔时代的技术创新[J]. 电子与封装, 2020, 20(12): 120101.
[5] 杨晖. 后摩尔时代Chiplet技术的演进与挑战[J]. 集成电路应用, 2020, 37(5): 52-54.
[6] MADDEN L, WU E, KIM N, et al. Advancing high performance heterogeneous integration through die stacking[C]// 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), Bardeaux, 2012: 18-24.
[7] LAU J H. Semiconductor Advanced Packaging[M]. Singapore: Springer Singapore, 2021.
[8] MAHAJAN R, SANE S. Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same: US8064224[P]. 2011-11-22.
[9] BRAUNISCH H, ALEKSOV A, LOTZ S, et al. High-speed performance of Silicon Bridge die-to-die interconnects[C]// 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, San Jose, 2011: 95-98.
[10] AGARWAL R, CHENG P, SHAH P, et al. 3D packaging for heterogeneous integration[C]// 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), San Diego, 2022: 1103-1107.
[11] LAU J H. Evolution and outlook of TSV and 3D IC/Si integration[C]// 2010 12th Electronics Packaging Technology Conference, Singapore, 2010: 560-570.
[12] WANG M J, HUNG C Y, KAO C L, et al. TSV technology for 2.5D IC solution[C]// 2012 IEEE 62nd Electronic Components and Technology Conference, San Diego, 2012.
[13] GAMBINO J P, ADDERLY S A, KNICKERBOCKER J U. An overview of through-silicon-via technology and manufacturing challenges[J]. Microelectronic Engineering, 2015, 135(3): 73-106.
[14] RAO V S, WEE H S, VINCENT L W S, et al. TSV interposer fabrication for 3D IC packaging[C]// 2009 11th Electronics Packaging Technology Conference, Singapore, 2009: 431-437.
[15] MURAYAMA K, AIZAWA M, HARA K, et al. Warpage control of silicon interposer for 2.5D package application[C]// 2013 IEEE 63rd Electronic Components and Technology Conference, Las Vegas, 2013: 879-884.
[16] HO S W, DING M Z, LIM P S, et al. 2.5D through silicon interposer package fabrication by chip-on-wafer (CoW) approach[C]// 2014 IEEE 16th Electronics Packaging Technology Conference (EPTC), Singapore, 2014: 679-683.
[17] ZHANG X W, LIN J K, WICKRAMANAYAKA S, et al. Heterogeneous 2.5D integration on through silicon interposer[J]. Applied Physics Reviews, 2015, 2(2): 021308.
[18] YOU J W, LI J, HO D, et al. Electrical performances of fan-out embedded bridge[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, 2021: 2030-2034.
[19] LIN J, CHUNG C K, LIN C F, et al. Scalable chiplet package using fan-out embedded bridge[C]// 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, 2020.
[20] LIU S L B, KAO N, SHIH T, et al. Fan-out embedded bridge solution in HPC application[C]// 2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC), Singapore, 2021.
[21] Highlights of the TSMC Technology Symposium–Part 2[EB/OL]. (2020-09-07) [2023-01-12]. http://www. semiwiki.com/semiconductor-manufacturers/tsmc/290560- Highlights of the TSMC Technology Symposium-Part 2.
[22] MAHAJAN R, QIAN Z G, VISWANATH R S, et al. Embedded multidie interconnect bridge-a localized, high-density multichip packaging interconnect[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2019, 9(10): 1952-1962.
[23] HU D C, TSENG T J, CHEN Y H, et al. An innovative embedded interposer carrier for high density interconnection[C]// 2013 IEEE 63rd Electronic Components and Technology Conference, Las Vegas, 2013: 1332-1335.
[24] MA S Y, CHANG J W, WANG J, et al. Progress and applications of embedded system in chip (eSinC?) technology[C]// 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, 2020: 1671-1676.
[25] LAU J H, LEE C K, ZHAN C J, et al. Low-cost TSH (through-silicon hole) interposers for 3D IC integration[C]// 2014 IEEE 64th Electronic Components and Technology Conference (ECTC), Orlando, 2014: 290-296.
[26] COUDRAIN P, CHAUSSE P, ARNAUD L, et al. Active interposer technology for chiplet-based advanced 3D system architectures[C]// 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), Las Vegas, 2019: 569-578.
[27] LAU J H. Recent advances and trends in advanced packaging[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2022, 12(2): 228-252.
[28] KURITA Y, MATSUI S, TAKAHASHI N, et al. A 3D stacked memory integrated on a logic device using SMAFTI technology[C]// 2007 Proceedings 57th Electronic Components and Technology Conference, Sparks, 2007: 821-829.
[29] INGERLY D B, ENAMUL K, GOMES W, et al. Foveros: 3D integration and the use of face-to-face chip stacking for logic devices[C]// 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco 2019: 466-469.
[30] GOMES W, MORGAN S, PHELPS B, et al. Meteor lake and arrow lake intel next-gen 3D client architecture platform with foveros[C]// 2022 IEEE Hot Chips 34 Symposium (HCS), Santa Clara, 2022.
[31] CHEN M F, CHEN F C, CHIOU W C, et al. System on integrated chips (SoIC(TM) for 3D heterogeneous integration[C]// 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), Las Vegas, 2019: 594-599.
[32] CHENG Y K, LEE F, CHEN M F, et al. Next-generation design and technology co-optimization (DTCO) of system on integrated chip (SoIC) for mobile and HPC applications[C]// 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2020.
[33] YU D. TSMC packaging technologies for chiplets and 3D[C]// 2021 IEEE Hot Chips 33 Symposium(HCS), Santa Clara, IEEE, 2021.
[34] MAHAJAN R, SANKMAN R, PATEL N, et al. Embedded multi-die interconnect bridge (EMIB): A high density, high bandwidth packaging interconnect[C]// 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, 2016: 557-565.

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