[1] LI T, HOU J, YAN J L, et al. Chiplet heterogeneous integration technology—status and challenges[J]. Electronics, 2020, 9(4): 670. [2] DESAI S B, MADHVAPATHY S R, SACHID A B, et al. MoS2 transistors with 1-nanometer gate lengths[J]. Science, 2016, 354(6308): 99-102. [3] 刘汉诚. 异构集成技术[M]. 北京: 机械工业出版社, 2023. [4] HUANG P K, LU C Y, WEI W H, et al. Wafer level system integration of the fifth generation CoWoS?-S with high performance Si interposer at 2500 mm2[C]//2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2021: 101-104. [5] MIN M, KADIVAR S. Accelerating innovations in the new era of HPC, 5G and networking with advanced 3D packaging technologies[C]//2020 International Wafer Level Packaging Conference (IWLPC), San Jose, CA, USA, 2020: 1-6. [6] CHEN M F, TSAI C H, KU T, et al. Low temperature SoIC bonding and stacking technology for 12-/ 16-hi high bandwidth memory (HBM)[J]. IEEE Transactions on Electron Devices, 2020, 67(12): 5343-5348. [7] MAHAJAN R, SANKMAN R, Aygun K, et al. Embedded multi-die interconnect bridge (EMIB): a high density, high bandwidth packaging interconnect[M/OL]// KESER B, KROEHNERT S. Advances in embedded and fan-out wafer-level packaging technologies. New York: John Wiley & Sons, Inc., 2019: 487-499(2019-01-18)[2024-05-01]. https://onlinelibrary.wiley.com/doi/book/10.1002/9781119313991. [8] 沈丛. 台积电、英特尔、三星竞逐3D封装市场[N/OL].中国电子报(2024-02-27)[2024-04-08]. https://epaper.cena.com.cn/pc/content/202402/27/content_9525.html. [9] CHEN H J, BIAN Z Y, LIU T, et al. Study on the manufacturability of X dimension fan out integration package with organic RDLs (XDFOI-O)[J]. Journal of Microelectronics and Electronic Packaging, 2024, 21(1): 14-19. [10] 熊国杰, 张津铭, 贺光辉. 一种面向Chiplet互连的高效传输协议设计与实现[J]. 计算机工程与科学, 2023, 45(8): 1339-1346. [11] 张墅野, 邵建航, 何鹏. 封装技术在5G时代的创新与应用[J]. 微电子学与计算机, 2023, 40(11): 9-21. [12] YU D. Embedded silicon fan-out (eSiFO?) technology for wafer-level system integration[J]. Advances in Embedded and Fan-Out Wafer Level Packaging Technologies, 2019: 169-184. [13] SHEN W W, CHEN K N. Three-dimensional integrated circuit (3D IC) key technology: through-silicon via (TSV)[J]. Nanoscale Research Letters, 2017, 12(1): 56. [14] LAU J H. Recent advances and trends in multiple system and heterogeneous integration with TSV-less interposers[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2022, 12(8): 1271-1281. [15] SHOREY A B, LU R. Progress and application of through glass via (TGV) technology[C]//Proceedings of the Pan Pacific Microelectronics Symposium (Pan Pacific), Big Island, HI, USA, 2016: 1-6. [16] LIN Y H, YEW M C, CHEN S M, et al. Multilayer RDL interposer for heterogeneous device and module integration[C]//Proceedings of the IEEE 69th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA, 2019: 931-936. [17] LIANG S W, WU G C Y, YEE K C, et al. High performance and energy efficient computing with advanced SoIC? scaling[C]//Proceedings of the IEEE 72nd Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2022: 1090-1094. [18] 项少林, 郭茂, 蒲菠, 等. Chiplet技术发展现状[J]. 科技导报, 2023, 41(19): 113-131. [19] 陈力, 杨晓锋, 于大全. 玻璃通孔技术研究进展[J]. 电子与封装, 2021, 21(4): 040101. [20] 李沛杰, 刘勤让, 陈艇, 等. 异构集成互连接口研究综述[J]. 集成电路与嵌入式系统, 2024, 24(2): 31-40. [21] MALTENBERGER T, ILIC I, TOLOVSKI I, et al. Evaluating multi-GPU sorting with modern interconnects[C]//Proceedings of the 2022 International Conference on Management of Data, Philadelphia PA USA, 2022: 1795-1809. [22] 许晋彰, 景乃锋, 蒋剑飞. 一种面向多处理器互连的高速串行传输系统设计[J]. 微电子学与计算机, 2020, 37(8): 16-20, 26. [23] DAS SHARMA D, PASDAST G, QIAN Z G, et al. Universal chiplet interconnect express (UCIe): an open industry standard for innovations with Chiplets at package level[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2022, 12(9): 1423-1431. [24] DAS SHARMA D. System on a package innovations with universal Chiplet interconnect express (UCIe) interconnect[J]. IEEE Micro, 2023, 43(2): 76-85. [25] 王俊, 杨晓飞. 光子芯片研究进展及展望[J]. 世界科学, 2020(12): 29-31. [26] 沈湘, 于杰平, 王丽. 光子芯片领域研究重点和发展趋势分析[J]. 数据与计算发展前沿, 2023, 5(4): 3-15. [27] 陆延青, 肖敏, 彭茹雯, 等. 人工微结构中的量子、类量子效应及功能集成光子芯片研究进展[J]. 中国基础科学, 2020, 22(1): 11-24. [28] 卞玲艳, 曾艳萍, 蔡莹, 等. 大数据时代光电共封技术的机遇与挑战[J]. 激光与光电子学进展, 2024, 61(9): 0900006. [29] SNIGIREV V, RIEDHAUSER A, LIHACHEV G, et al. Ultrafast tunable lasers using lithium niobate integrated photonics[J]. Nature, 2023, 615(7952): 411-417. [30] KATARI M, KRISHNAMOORTHY G, JEYARAMAN J. Novel materials and processes for miniaturization in semiconductor packaging[J]. Journal of Artificial Intelligence General Science (JAIGS) ISSN: 3006-4023, 2024, 2(1): 251-271. [31] REN R J, GAO J, ZHOU W H, et al. 128 identical quantum sources integrated on a single silica chip[J]. Physical Review Applied, 2021, 16(5): 054026. [32] 洪伟, 余超, 陈继新, 等. 5G及其演进中的毫米波技术[J]. 微波学报, 2020, 36(1): 12-16. [33] DUAN Z M, WU B W, WANG Y, et al. A 76–81 GHz 2×8 MIMO radar transceiver with broadband fast chirp generation and 16-antenna-in-package virtual array[J]. IEEE Journal of Solid-State Circuits, 2023, 58(11): 3103-3112. [34] SINGH C, SHARMA C, TRIPATHI S, et al. A comprehensive survey on millimeter wave antennas at 30/60/120 GHz: design, challenges and applications[J]. Wireless Personal Communications, 2023, 133(3): 1547-1584. [35] ZHANG Y P. Differential antennas: fundamentals and applications[J]. Electromagnetic Science, 2023, 1(1): 0010021. [36] JIN C, SEKHAR V N, BAO X Y, et al. Antenna-in-package design based on wafer-level packaging with through silicon via technology[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2013, 3(9): 1498-1505. [37] YU T, ZHANG X D, CHEN L, et al. Development of embedded glass wafer fan-out package with 2D antenna arrays for 77GHz millimeter-wave chip[C]//2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2020: 31-36.[LinkOut] [38] LIM S P S, CHONG S C, WEE D H S, et al. Assembly challenges and demonstrations of ultra-large Antenna in Package for Automotive Radar applications[C]//2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2022: 635-642.[LinkOut] [39] 郭继旺, 尹文婷, 谈玲燕, 等. Chiplet异构集成微系统的EDA工具发展综述[J]. 微电子学与计算机, 2023, 40(11): 53-60. [40] LI S. SiP and advanced packaging technology[M]//LI S. MicroSystem Based on SiP Technology. Singapore: Springer, 2022: 117-154. [41] PENTAPATI S, LIM S K. Heterogeneous monolithic 3-D IC designs: challenges, EDA solutions, and power, performance, cost tradeoffs[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024, 32(3): 413-421. [42] 郭继旺,尹文婷,谈玲燕,等.Chiplet异构集成微系统的EDA工具发展综述[J]. 微电子学与计算机,2023,40(11):53-60. [43] KATZ E, AVITAL M, WEIZMAN Y, et al. Analytical side channel EM models, extending simulation abilities for ICs, and linking physical models to cryptographic metrics[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023, 42(12): 4463-4476. [44] 刘军, 高爽, 汪曾达, 等. 射频异构集成微系统多层级协同仿真建模与PDK技术综述[J]. 微电子学与计算机, 2024, 41(1): 11-25. [45] 汪志强, 杨凝, 张劭春, 等. 异质异构集成微系统可靠性技术发展的挑战和机遇[J]. 微电子学与计算机, 2023, 40(11): 61-71. [46] CHE F X, HO D, CHAI T C. Study on warpage and reliability of fan-out interposer technology[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2019, 9(4): 786-796. [47] 孙国立, 公颜鹏, 侯传涛, 等. 基于RVE-子模型法的多尺度封装结构分析方法[J]. 强度与环境, 2022, 49(5): 88-93. [48] WANG H Y, MA J S, YANG Y D, et al. A review of system-in-package technologies: application and reliability of advanced packaging[J]. Micromachines, 2023, 14(6): 1149. [49] WANG Z Y, SUN J B, GOKSOY A, et al. Exploiting 2.5D/3D heterogeneous integration for AI computing[C]//Proceedings of the 29th Asia and South Pacific Design Automation Conference (ASP-DAC), Incheon, Korea, 2024: 758-764. |