中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2025, Vol. 25 ›› Issue (11): 110302 . doi: 10.16257/j.cnki.1681-1070.2025.0131

• 电路与系统 • 上一篇    下一篇

28 nm CMOS工艺下电平移位器的对比研究*

许嘉航,白春风   

  1. 苏州大学电子信息学院,江苏 苏州 215006
  • 收稿日期:2025-04-02 出版日期:2025-11-28 发布日期:2025-11-28
  • 作者简介:许嘉航(2002—),男,上海人,硕士研究生,研究方向为模拟集成电路的设计与分析。

Comparison and Research of Level Shifter in 28 nm CMOS Process

XU Jiahang, BAI Chunfeng   

  1. School of Electronic Information, SoochowUniversity, Suzhou 215006, China
  • Received:2025-04-02 Online:2025-11-28 Published:2025-11-28

摘要: 电平移位器(LS)是解决跨电压域通信的关键模块。基于28 nm CMOS工艺,调整LS结构的器件参数,通过瞬态仿真、工艺角分析与蒙特卡罗仿真,分析了LS实现电路的延迟、功耗及稳健性。结果表明,竞争抑制Ⅰ型差分层叠电压开关(DCVS)与威尔逊电流镜(WCM)结构在1 GHz高频输入下综合性能最优,延迟分别低至68.21 ps与99.86 ps,延迟功耗积分别低至1 066.11 ns·nW与1 558.25 ns·nW。

关键词: 电平移位器, CMOS, 延迟, 对比

Abstract: Level shifter (LS) is a key module for solving cross voltage domain communication. Based on a 28 nm CMOS process, the device parameters of LS structures are adjusted. The delay, power consumption, and robustness of LS implementation circuits are then systematically quantified through transient simulation, process corner analysis, and Monte Carlo simulation. Results indicate that the competitive suppression type Ⅰ differential layer stacked voltage switch (DCVS) and Wilson current mirror (WCM) structures are identified as having the optimal overall performance at a 1 GHz high-frequency input, with delays as low as 68.21 ps and 99.86 ps, and power-delay products as low as 1 066.11 ns·nW and 1 558.25 ns·nW, respectively.

Key words: level shifter, CMOS, delay, comparison

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