采样保持电路中全差分增益提高放大器设计

doi:10.16257/j.cnki.1681-1070.2017.0108

电子与封装 ›› 2017, Vol. 17 ›› Issue (9): 19 -22. doi: 10.16257/j.cnki.1681-1070.2017.0108

采样保持电路中全差分增益提高放大器设计

钱黎明，魏敬和

中国电子科技集团公司第五十八研究所，江苏无锡 214072

出版日期:2017-09-20 发布日期:2017-09-20
作者简介:钱黎明（1981—），男，安徽芜湖人，硕士，现在中国电子科技集团公司第五十八研究所从事系统芯片SoC设计与研发工作。

Design of Fully Differential Gain Boosted OPAMP Dedicated to Sample and Hold Circuit

QIAN Liming, WEI Jinhe

China Electronic Technology Group Corporation No.58 Research Institute, Wuxi 214072, China

Online:2017-09-20 Published:2017-09-20

摘要/Abstract

摘要： 介绍了一种全差分增益增强CMOS运算放大器的设计和实现。该放大器用于12位20 MHz采样频率的流水线模/数转换器(A/D)的采样保持电路。为了实现大的输入共模范围,采用折叠式共源共栅放大器。主放大器采用开关电容共模反馈电路,辅助放大器则采用简单的连续时间共模反馈电路。该放大器采用CMOS 0.5μm工艺,电源电压为3.3 V。Cadence Spectre仿真结果显示,在负载为6 p F的情况下,其增益为99 d B,单位增益带宽为318 MHz,相位裕度为53°。

关键词: 增益提高, 共模反馈, 采样保持电路

Abstract: A kind of gain boosted fully differential CMOS operational amplifier is introduced in this paper. It is used for the Sample and Hold (S&H) circuits of a 12 bit 20 MHz pipeline A/D convertor. The main amplifier is folded cascode to obtain a large range of input common mode voltage. The switched capacitor Common Mode Feedback circuit (CMFB) is adopted in main amplifier, while simplecontinuous time CMFB is implemented in the auxiliary amplifier to reduce power consumption and simplify the circuit . The amplifier is designed with CMOS 0.5 μm process under 3.3 V power supply. Cadence Spectre simulation result shows that the amplifier has achived the DC gain of 99 dB, the gain bandwidth of 318 MHz and the phase margin of 53 degree at the load of 6 pF.

Key words: gain_boosted, PLL, CMFB

中图分类号:

TN722

钱黎明，魏敬和. 采样保持电路中全差分增益提高放大器设计[J]. 电子与封装, 2017, 17(9): 19 -22.

QIAN Liming, WEI Jinhe. Design of Fully Differential Gain Boosted OPAMP Dedicated to Sample and Hold Circuit[J]. Electronics & Packaging, 2017, 17(9): 19 -22.

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采样保持电路中全差分增益提高放大器设计

Design of Fully Differential Gain Boosted OPAMP Dedicated to Sample and Hold Circuit

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