中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2018, Vol. 18 ›› Issue (4): 26 -29. doi: 10.16257/j.cnki.1681-1070.2018.0042

• 电路设计 • 上一篇    下一篇

BLE级FPGA布局实现及验证

惠 锋1,许 慧1,虞 健1,王新晨2   

  1. 1.无锡中微亿芯有限公司,江苏无锡 214072;2.中国电子科技集团公司第五十八研究所,江苏无锡 214072
  • 收稿日期:2017-11-02 出版日期:2018-04-24 发布日期:2018-04-24
  • 作者简介:惠 锋(1977—),男,江苏无锡人,本科学历,软件工程师,现从事EDA软件领域工作。

Implementation and Verification for BLE Level FPGA Placement

HUI Feng1,XU hui1,YU Jian1,WANG Xinchen2   

  1. 1.East Technologies Inc.,Wuxi 214072,China;2.China Electronics Technology Group Corporation No.58 Research Institute,Wuxi 214072,China
  • Received:2017-11-02 Online:2018-04-24 Published:2018-04-24

摘要: 布局是EDA流程中至关重要的环节,布局质量的好坏直接影响了其后的布线过程,乃至布线完成后整个电路的性能。传统的FPGA布局中以CLB为最小单元,一旦打包完成,CLB中的配置不再改变。实现了BLE级的FPGA布局,并把布局结果转换为XDL格式文件,使用Xilinx工具验证其正确性。

关键词: FPGA, BLE, 布局

Abstract: Placement is of great importance in EDA steps,the quality of placement has a direct influence on routing step followed,or even the performance of the entire circuit after routing.In the traditional FPGA placement,CLB is the base unit,and once packing is finished,the configuration of the CLB will never change.In this paper,a BLE level FPGA placement tool is implemented,then translate the result to XDL file,in the end itisverified through the tools of Xilinx.

Key words: FPGA, BLE, placement

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