关键词: 流水线-逐次逼近型ADC, 异步时序, 系统结构, 动态放大器

Abstract: Analog to Digital Converter (ADC) plays a key role in the field of modern signal processing. Considering the performance indicators such as resolution, sampling rate, and power consumption, Pipelined-SAR ADCs have obvious advantages. This paper proposes a pipeline-successive approximation ADC with asynchronous timing diagram. Based on the traditional control method, this control method improves the method of generating control signals required for ADC operation and the control method of the circuit, streamlines unnecessary control signals to improve time utilization efficiency, and adds inter-stage handshake signals to ensure the stability of the ADC. This method is applied to 14 bit-800 Msps Pipeline-SAR ADC, and the effective number of bits (Enob) can reach 12 bit.

Key words: pipelined-successive approximation register ADC, asynchronous timing diagram, system structure, dynamic amplifier