中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

导航

电子与封装 ›› 2019, Vol. 19 ›› Issue (11): 9 -13. doi: 10.16257/j.cnki.1681-1070.2019.1103

• 封装、组装与测试 • 上一篇    下一篇

常规锡膏回流焊接空洞的分析与解决

杨建伟   

  1. 广东气派科技有限公司,广东 东莞 523000
  • 出版日期:2019-11-20 发布日期:2019-12-25
  • 作者简介:杨建伟(1981—),男,陕西安康人,本科,现任广东气派科技有限公司研发经理,从事半导体封装研发工作。

Study of Solder Void on Traditional Solder Print and Reflow Process in Package

YANG Jianwei   

  1. Guangdong Chippacking Technology Ltd. , Dongguan 523000, China
  • Online:2019-11-20 Published:2019-12-25

摘要: 锡膏回流焊是半导体封装中组装工艺之一,较大焊接面积中焊接空洞是最常见和最难解决的问题之一。通过对锡膏印刷回流焊工艺特性的分析和相关性试验,排查出造成空洞的主要影响因素,运用实验设计(DOE)优化工艺参数、减少焊接空洞。为满足芯片焊接空洞要求,采用二次印刷回流新工艺,将芯片焊接空洞面积率降低到5%以内,解决因空洞引起的芯片裂损问题,为常规低成本锡膏回流焊接工艺的焊接空洞问题改善提供了参考。

关键词: 锡膏, 焊接空洞, 回流焊

Abstract: Solder print and reflow is one important process in package assembly, and solder void is a very common and serious issue in traditional reflow process. It’s very difficult to solve especially for some QFN and die with bigger solder area. By analyzing the process properties, the root-cause of solder void is identified. DOE is used to find and optimize the main effect factors to improve solder void. By introducing two times reflow process and optimized parameters, the solder void coverage is reduced to less than 5%, and die crack issue which cause as solder void is solved, which provides the solution of solder void for common solder print and reflow process.

Key words: solder paste, solder void, reflow

中图分类号: