中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2017, Vol. 17 ›› Issue (9): 41 -43. doi: 10.16257/j.cnki.1681-1070.2017.0113

• 微电子制造与可靠性 • 上一篇    下一篇

反应离子刻蚀硅槽工艺研究

赵金茹,蒋大伟,陈杰   

  1. 中国电子科技集团公司第58研究所,江苏 无锡 214072
  • 出版日期:2017-09-20 发布日期:2017-09-20
  • 作者简介:赵金茹(1983—),女,辽宁省海城人,2006年毕业于辽宁大学,现为中国电子科技集团公司第五十八研究所二部腐蚀工艺工程师,主要从事刻蚀工艺的研究与开发。

Trench of Reactive Ion Etching Technology Research

ZHAO Jinru, JIANG Dawei, CHEN Jie   

  1. China Electronics Technology Group Corporation No.58 Research Institute, Wuxi 214072,China
  • Online:2017-09-20 Published:2017-09-20

摘要: 在CMOS多晶硅刻蚀工艺的基础上进行工艺开发,采用氯气和溴化氢气体进行硅槽刻蚀。通过对功率、压力、气体流量等工艺参数拉偏,用扫描电子显微镜观察硅槽侧壁形貌,分析各参数在反应离子刻蚀中所起到的作用,得到对硅槽形貌影响较大的因素,最终得到一种能够与CMOS工艺兼容的硅槽刻蚀方法。该方法能够制作出深度6μm、深宽比4∶1、侧壁光滑的硅槽,可以用于光电继电器、硅电容等新型器件的研发。

关键词: 硅槽刻蚀, 氯气, 溴化氢, 反应离子刻蚀, 光电继电器, 硅电容

Abstract: The purpose of this study is to develop the process based on polysilicon etching process,Using CL2 and HBR gas for trench etching. With experiments, adjusting the power, pressure, gas flow process window. with the helping of scanning electron microscope, checking the shape of the sidewall of the trench,analysis of the function of each parameters, the factors of affecting trench are obtained. Finally, a trench etching method which can be compatible with CMOS is obtained, successfully produced the depth of 6μm, sidewall smooth trench, reseached for Semiconductors such as photoelectric relay and silicon capacitor.

Key words: trench etching, CL2, HBr, reactive ion etching, photoelectric relay, silicon capacitor

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