中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2018, Vol. 18 ›› Issue (5): 8 -11. doi: 10.16257/j.cnki.1681-1070.2018.0049

• 封装、组装与测试 • 上一篇    下一篇

FPGA测试压缩技术研究

解维坤1,陈 龙1,黄 晋1,肖艳梅2   

  1. 1.中国电子科技集团公司第五十八研究所,江苏无锡 214035;2.江南大学物联网工程学院,江苏无锡 214122
  • 收稿日期:2018-01-19 出版日期:2018-05-20 发布日期:2018-05-20
  • 作者简介:解维坤(1980—),男,山东人,硕士研究生,2008年毕业于厦门大学控制理论与控制工程专业,现任职于中国电子科技集团公司第五十八研究所检测事业部,研究方向为FPGA等可编程器件的测试技术。

Research on Test Compression Technology of FPGA

XIE Weikun1,CHEN Long1,HUANG Jin1,XIAO Yanmei2   

  1. 1.China Electronics Technology Group Corporation No.58 Research Institute,Wuxi 214035,China;2.School of Internet of Things Engineering,Jiangnan University,Wuxi 214122,China
  • Received:2018-01-19 Online:2018-05-20 Published:2018-05-20

摘要: 随着FPGA规模不断增大,配置码越来越大,配置时间也越来越长,因此降低测试时间、提高测试效率具有十分重要的意义。主要从位流压缩和向量加载角度出发,研究了基于多帧写FPGA位流压缩、基于ATE的X模式和Multiport方式的测试压缩等多种测试压缩方法。以Xilinx公司Virtex-5系列FPGA-XC5VLX155T为例进行了测试验证。测试结果证明,采用测试压缩方法可使单颗FPGA的测试时间至少节省25.5 s,这些方法可大大降低对测试系统向量空间的需求,缩短FPGA的测试配置时间、提高测试效率,同时对其他类型数字电路的测试也有借鉴作用。

关键词: FPGA, 配置时间, 压缩测试, ATE

Abstract: With the increase in the size of the FPGA,the size of the configuration code is getting bigger and the configuration time is getting longer for FPGA test.Therefore,reducing test time has great significance to improve the test efficiency.On the basis of bit stream compression and vector loading,a variety of test compression methods,including FPGA bit stream compression based on multi frame writing,X mode test compression and multiport test compression based on ATE,are investigated.The test for Xilinx Virtex-5 FPGA XC5VLX155T illustrated those methods.The testresults show thatthe testcompression methods can reduce the test time of a single FPGA at least 25.5 s,greatly reduce the requirement for the vector space of the test system,shorten the test configuration time and improve the test efficiency of FPGA.The proposed methods also provide a good reference forother typesofdigitalcircuittesting.

Key words: FPGA, configuration time, compression test, ATE

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