关键词: ADC测试, FPGA, 数模混合仿真, 测试资源优化, 测试方法

Abstract: With the development of ultra deep submicron technology and the design of SoC based on IP core, the logic function of the chip is becoming more and more complex, and more pins and testing resources are needed.In order to meet the needs of different customers, the pin number of the chip is flexible, which directly leads to the limitation on the use of the chip test resources.The use of less hardware resources to complete the complex logic function testis one of the core technologies of the logic design of the chip test. This paper mainly introduces the optimization of test resources for ADC. First, the traditional ADC test structure and its limitations are introduced.Then, the test structure after ADC optimization is introduced, so that it can ensure test flexibility under the condition of fewer chip pins. Finally, on this basis, the ADC digital analog simulation environment is built, and the basic functions of ADC are simulated and tested by using NC-SIM software.

Key words: ADC test, FPGA, ADC digital analog simulation, optimization of test resources, test method