关键词: 配置存储器, FPGA, 可变容量, Flash, 存储器内建自测试

Abstract: An FPGA configuration memory is designed with 0.18 μm 2P6M Flash process. It provides serial and parallel stream loading modes for SRAM FPGAs. The maximum working frequency is 50 MHz, and it has the advantages of variable storage capacity and high reliability. The memory capacity variability of the FPGA configuration chip is realized by designing an address detection circuit, and the application range of the FPGA configuration chip is improved. By designing a two-mode reset circuit,the chip is more suitable for complex power supply environment, and the reliability of power-on reset is improved.Memory build in self-test (MBIST) circuit is designed to realize the self-test of Flash full address storage space and efficient screening of the circuit, the test time of the chip is reduced, and the reliability of the configuration chip storage space is improved.

Key words: configuration memory, FPGA, variable capacity, Flash, memory build in self-test