中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2024, Vol. 24 ›› Issue (1): 010205 . doi: 10.16257/j.cnki.1681-1070.2024.0012

• 封装、组装与测试 • 上一篇    下一篇

时钟缓冲器附加抖动分析

陈文涛;邵海洲;胡劲涵   

  1. 中国电子科技集团公司第五十八研究所,江苏 无锡? 214035
  • 收稿日期:2023-07-26 出版日期:2024-01-15 发布日期:2024-01-15
  • 作者简介:陈文涛(1983—),男,陕西汉中人,硕士,工程师,主要研究方向为射频SiP系统设计与测试。

Analysis of Additive Jitter in Clock Buffers

CHEN Wentao, SHAO Haizhou, HU Jinhan   

  1. China Electronics Technology GroupCorporation No.58 Research Institute,Wuxi 214035, China
  • Received:2023-07-26 Online:2024-01-15 Published:2024-01-15

摘要: 附加抖动是时钟缓冲器的一项关键指标。从相位噪声的角度对附加抖动计算公式进行了理论推导,证明了附加抖动计算公式的正确性。通过对时钟缓冲器的实际测试,从实测角度对附加抖动计算公式的推导进行了验证。结合附加抖动计算公式,给出了时钟缓冲器附加抖动测试中的注意事项,以保证测试结果的准确性。

关键词: 附加抖动, 相位噪声, 时钟缓冲器

Abstract: Additive jitter is a key indicator for clock buffers. The theoretical derivation of the additive jitter calculation formula from the perspective of phase noise is carried out, and the correctness of the additive jitter calculation formula is proved. Through the actual tests of the clock buffers, the derivation of the additive jitter calculation formula is verified from the perspective of actual measurements. Combined with the calculation formula for additive jitter, precautions in the additive jitter test of clock buffers are provided to ensure the accuracy of the test results.

Key words: additive jitter, phase noise, clock buffers

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