单粒子翻转效应的FPGA模拟技术*

doi:10.16257/j.cnki.1681-1070.2021.0911

摘要/Abstract

摘要： 随着半导体工艺节点遵循着摩尔定律逐渐缩小，空间环境中辐射诱发的单粒子效应（Single Event Effect, SEE）对集成电路造成的影响却在不断增加。单粒子翻转（Single Event Upset, SEU）效应是最为普遍的单粒子效应，表现为电路存储单元和时序逻辑中的逻辑位翻转，在集成电路中常采用故障注入技术来模拟单粒子翻转效应。因此，重点研究了目前较为常用的3种故障注入技术，分别是现场可编程门阵列（Field Programmable Gate Array, FPGA）重配置，扫描链和旁路电路，分析了各自的优势和不足，并对未来的发展趋势进行了预测。

关键词: 单粒子效应, 单粒子翻转, 超大规模集成电路, FPGA模拟, 故障注入

Abstract: Following Moore's law, the character size of semiconductor process node is decreasing, and the impact of radiation-induced single event effect (SEE) on integrated circuits is increasing. The single event upset (SEU) effect, which represents the bit flip in the memory cell and sequential logic, has a higher probability of occurrence in SEE. Fault injection technique is often adopted to emulate SEU effect in integrated circuit. Therefore, three fault injection technologies which are dynamic reconfiguration, scan chain and bypass circuit are studied. In addition, the advantages and disadvantages of these methods are also analyzed. The general trend of field programmable gate array (FPGA) emulation technology is made at last.

Key words: singleeventeffect, singleeventupset, VLSI, FPGAemulation, faultinjection

中图分类号:

TN47

陈鑫;施聿哲;白雨鑫;陈凯;张智维;张颖. 单粒子翻转效应的FPGA模拟技术^*[J]. 电子与封装, 2021, 21(9): 090402 .

CHEN Xin, SHI Yuzhe, BAI Yuxin, CHEN Kai, ZHANG Zhiwei, ZHANG Ying. FPGA EmulationTechnologyforSingle Event Upset[J]. Electronics & Packaging, 2021, 21(9): 090402 .

参考文献

[1] INGUIMBER C, ECOFFET R, FALGUERE D. Electron induced SEUs: Microdosimetry in nanometric volumes[J]. IEEE Transactions on Nuclear Science, 2015, 62(6): 2846-2852.
[2] Semiconductor Industry Association. International technology roadmap for semiconductors 2011 edition executive summary[M]. Washington, DC: Semiconductor Industry Association, 2011:22.
[3] 薛玉雄, 杨生胜, 把得东,等. 空间辐射环境诱发航天器故障或异常分析[J]. 真空与低温, 2012, 18(2): 63-70.
[4] 刘必慰. 集成电路单粒子效应建模与加固方法研究[D].长沙:国防科技大学, 2009.
[5] 何安林, 郭刚, 沈东军, 等. 65 nm工艺SRAM低能质子单粒子翻转错误率预估[J]. 原子能科学技术, 2019, 53(2): 366-372.
[6] CHEN Q, CHEN L, HIEMSTRA D M, et al. Single event upset characterization of the stratix IV field programmable gate array using proton irradiation[C]// 2018 IEEE Radiation Effects Data Workshop (REDW). IEEE, 2018: 1-5.
[7] MAILLARD P, HART M, BARTON J, et al. Neutron, 64 MeV proton, thermal neutron and alpha single-event upset characterization of Xilinx 20 nm UltraScale Kintex FPGA[C]//2015 IEEE Radiation Effects Data Workshop (REDW). IEEE, 2015: 1-5.
[8] 孙峻朝, 王建莹, 杨孝宗. 故障注入方法与工具的研究现状[J]. 宇航学报, 2001, 22(1):99-104.
[9] WANG Q, LIU H, WANG S, et al. TCAD simulation of single-event-transient effects in L-shaped channel tunneling field-effect transistors[J]. IEEE Transactions on Nuclear Science, 2018, 65(8): 2250-2259.
[10] BHUVA B L, PAULOS J J, GYURCSIK R S, et al. Switch-level simulation of total dose effects on CMOS VLSI circuits[J]. IEEE transactions on computer-aided design of integrated circuits and systems, 1989, 8(9): 933-938.
[11] SEWARD S R, LALA P K. Fault injection in digital logic circuits at the VHDL level[C]// 9th IEEE on-Line Testing Symposium, 2003. IOLTS 2003. IEEE, 2003: 161.
[12] 谭兰芳. 面向单粒子效应的软件故障注入技术研究[D]. 长沙：国防科学技术大学, 2008.
[13] 杨道宁. SRAM型FPGA单粒子效应故障注入测试方法关键技术研究[D]. 长沙：国防科学技术大学, 2013.
[14] ITURBE X, AZKARATE M, MARTINEZ I, et al. A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs[C]// 2009 International Conference on Field Programmable Logic and Applications. IEEE, 2009: 569-573.
[15] XIE Y, CHEN H, XIE Y Z, et al. An automated FPGA-based fault injection platform for granularly-pipelined fault tolerant CORDIC[C]// 2018 International Conference on Field-Programmable Technology (FPT). IEEE, 2018: 370-373.
[16] ZHANG R, XIAO L, LI J, et al. A fast fault injection platform of multiple SEUs for SRAM-based FPGAs[C]// 2017 Prognostics and System Health Management Conference (PHM-Harbin), IEEE, 2017: 1-5.
[17] 芦浩. 基于动态重配置的航空总线单粒子翻转效应测试系统研究[D]. 天津：中国民航大学, 2019.
[18] Xilinx. Vivado design suite user guide: partial reconfiguration UG909(v2017.4)[EB/OL]. (2017-12-20) [2021-04-22]https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug909-vivado-partial-reconfiguration.pdf.
[19] ANTONI L, LEVEUGLE R, FEHER B. Using run-time reconfiguration for fault injection applications[J]. IEEE Transactions on Instrumentation and Measurement, 2003, 52(5): 1468-1473.
[20] ARANDA L A, SANCHES-MACIAN A, MAESTRO J A. ACME: A tool to improve configuration memory fault injection in SRAM-based FPGAs[J]. IEEE Access, 2019, 7: 128153-128161.
[21] 周盛雨. 基于FPGA的动态部分重构系统实现[D]. 北京：中国科学院大学, 2007.
[22] CIVERA P, MACCHIARULO L, REBAUDENGO M, et al. Exploiting circuit emulation for fast hardness evaluation[J]. IEEE Transactions on Nuclear Science, 2001, 48(6): 2210-2216.
[23] LOPEZ-ONGIL C, GARCIA-VALDERAS M, PORTELA-GARCIA M, et al. Autonomous fault emulation: A new FPGA-based acceleration system for hardness evaluation[J]. IEEE Transactions on Nuclear Science, 2007, 54(1): 252-261.
[24] 徐松. 基于FPGA的集成电路故障注入攻击硬件模拟方法研究[D]. 天津：天津大学, 2016.
[25] SHOKROLAH-SHIRAZI M, MIREMADI S G. FPGA-based fault injection into synthesizable verilog HDL models[C]// 2008 Second International Conference on Secure System Integration and Reliability Improvement. IEEE, 2008: 143-149.
[26] MANSOUR W, VELAZCO R. SEU fault-injection in VHDL-based processors: a case study[J]. Journal of Electronic Testing, 2013, 29(1): 87-94.
[27] SERRANO F, CLEMENTE J A, MECHA H. A methodology to emulate single event upsets in flip-flops using FPGAs through partial reconfiguration and instrumentation[J]. IEEE Transactions on Nuclear Science, 2015, 62(4): 1617-1624.
[28] MOUSAVI M, POURSHAGHAGHI H R, TAHGHIGHI M, et al. A generic methodology to compute design sensitivity to SEU in SRAM-based FPGA[C]// 2018 21st Euromicro Conference on Digital System Design (DSD). IEEE, 2018: 221-228.
[29] MANSOUR W, VELAZCO R. An automated SEU fault-injection method and tool for HDL-based designs[J]. IEEE Transactions on Nuclear Science, 2013, 60(4): 2728-2733.
[30] MANSOUR W, VELAZCO R, AYOUBI R, et al. A method and an automated tool to perform set fault-injection on HDL-based designs[C]// 2013 25th International Conference on Microelectronics (ICM). IEEE, 2013: 1-4.
[31] JANNING A, HEYSZL J, SUMPF F, et al. A cost-effective FPGA-based fault simulation environment[C]// 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography. IEEE, 2011: 21-31.
[32] 刘欢. Reprogramming by HWICAP[EB/OL]. (2019-10-26) [2021-04-22] https://github.com/FPGA-Networking/Low-Cost-and-Programmable-CRC.

中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

单粒子翻转效应的FPGA模拟技术^*

FPGA EmulationTechnologyforSingle Event Upset

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