中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2017, Vol. 17 ›› Issue (10): 21 -25. doi: 10.16257/j.cnki.1681-1070.2017.0120

• 电路设计 • 上一篇    下一篇

一种低电源电压的多通道UART设计

王雪萍1,张国华1,2,顾展宏2,卓 琳2   

  1. 1.江南大学物联网工程学院,江苏无锡 214122;2.中国电子科技集团公司第五十八研究所,江苏 无锡 214072
  • 收稿日期:2017-06-13 出版日期:2017-10-20 发布日期:2017-10-20
  • 作者简介:王雪萍(1991—),女,河南信阳人,硕士研究生,主要研究方向为集成电路设计。

Design of a Low Supply Voltage Multi-Channel UART

WANG Xueping1,ZHANG Guohua1,2,GU Zhanhong2,ZHUO Lin2   

  1. 1.Schoolof Internetof Things Engineering,Jiangnan University,Wuxi 214122,China;2.China Electronics Technology Corporation No.58 Research Institute,Wuxi 214072,China
  • Received:2017-06-13 Online:2017-10-20 Published:2017-10-20

摘要: 为了满足复杂控制场合中多点通讯、低功耗、高速率以及低错误率等的要求,提出了一个低电源电压的多通道通用异步收发器(URAT,Universal Asynchronous Receiver and Transmitter)设计方案。每个通道独立控制,发送端和接收端配置的FIFO(First In First Out)在高速数据传输期间可临时存储数据以免数据丢失。采用自上而下的设计方法,使用Cadence工具进行合成与仿真。测试结果表明,该电路满足设计要求,仿真波形验证了数据收发的完整性。

关键词: 低电源电压, UART, 多通道, FIFO

Abstract: A design scheme for low power supply voltage multi-channel UART is proposed to meet the need of multi-point communication,low power consumption,high speed and low error rate in the complex control occasions.Each channel is independently controlled,and the FIFO configured at the transmitter and receiver can temporarily store data during high-speed data transmission to avoid data loss.The circuit utilizes top-down design method and uses Cadence tool for synthesis and simulation.The test results show that the circuit meets the design requirements,and the simulation waveforms verify the integrity of data transceiver.

Key words: low supply voltage, UART, multi-channel, FIFO

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