面向信息处理应用的异构集成微系统综述*

doi:10.16257/j.cnki.1681-1070.2021.1002

摘要/Abstract

摘要： 摩尔定律发展趋缓，技术变道迫在眉睫，以功能集成为核心、融合不同工艺节点的异构集成微系统成为了后摩尔时代超越摩尔定律的重要途径，获得国内外的广泛关注。异构集成微系统满足了当今电子系统小型化、高集成、高性能的迫切需求，并且伴随着功能密度的不断提升能够持续为微电子技术的发展注入新的活力。在高性能计算飞速发展的今天，各行业对高性能信息处理、数据运算的需求快速增长，信息处理也成为了当前异构集成微系统应用最广泛、发展最迅速的领域之一。立足当今行业发展现状，针对异构集成微系统在信息处理领域的应用，从先进封装、接口标准、热管理、可靠性等方面介绍了后摩尔时代异构集成微系统关键技术的最新进展，梳理了面向信息处理应用的异构集成微系统典型产品，并讨论了异构集成微系统的未来发展趋势与难点。

关键词: ?异构集成, 微系统, 信息处理, 先进封装, 接口标准

Abstract: ?The development of Moore’s Law is slowing down, and the technical route needs to change urgently. Heterogeneous integration microsystem takes functional integration as the core, and can integrate different process nodes, which has become an important way to surpass Moore’s Law in the More than Moore rea and has gained extensive attention at home and abroad. Heterogeneous integration microsystem can meet the urgent needs of miniaturization, high integration and high performance of electronic systems, and with the continuous improvement of function density can continue to inject new vitality into the development of microelectronics technology. With the rapid development of high performance computing, the demand for high performance information processing and data operation is increasing rapidly in all industries. The information processing has become one of the most widely used and rapidly developed fields of heterogeneous integration microsystem. Based on the current development status of the industry, for the application of heterogeneous integration microsystem in the field of information processing, the latest developments in the key technologies of heterogeneous integration microsystem in the More than Moore rea are introduced in terms of advanced packaging, interface standards, thermal management, and reliability. The typical products of heterogeneous integration microsystem for information processing applications are summarized, and the future development trend and difficulties are discussed.

Key words: ?heterogeneousintegration, microsystem, informationprocessing, advancedpackaging, interfacestandard

中图分类号:

TN405.97

王梦雅, 丁涛杰, 顾林, 曾燕萍, 李居强, 张景辉, 张琦, 孙晓冬. 面向信息处理应用的异构集成微系统综述^*[J]. 电子与封装, 2021, 21(10): 100102 .

WANG Mengya, DING Taojie, GU Lin, ZENG Yanping, LI Juqiang, ZHANG Jinghui, ZHANG Qi, SUN Xiaodong. Overview of Heterogeneous IntegrationMicrosystem for Information Processing Applications[J]. Electronics & Packaging, 2021, 21(10): 100102 .

参考文献

[1] 北京未来芯片技术高精尖创新中心. 智能微系统技术白皮书[EB/OL]. (2020-12-16)[2021-10-09]. https://www.163.com/dy/article/FTV31BJ50511BHI0.html.
[2] HANCOCK T M, DEMMIN J C. Heterogeneous and 3D integration at DARPA[C]//2019 International 3D Systems Integration Conference (3DIC), Oct. 8-10, 2019, Sendai, Japan, 2019: 4047.
[3] 郝继山, 向伟玮. 微系统三维异质异构集成与应用[J]. 电子工艺技术, 2018, 39(6): 317-321.
[4] DRUCKER K, JANI D, AGARWAL I, et al. The open domain-specific architecture[C]// 2020 IEEE Symposium on High-Performance Interconnects (HOTI), Aug. 19-21, 2020, Piscataway, NJ, USA. IEEE, 2020: 25-32.
[5] TAYLOR G, FARJADRAD R, VINNAKOTA B. High capacity on-package physical link considerations[C]//2019 IEEE Symposium on High-Performance Interconnects (HOTI). Aug. 14-16, 2019, Santa Clara, CA, USA. IEEE, 2019: 19-22.
[6] VINNAKOTA B, AGARWAL I, DRUCKER K, et al. The open domain-specific architecture[J]. IEEE Micro, 2021, 41(1): 30-36.
[7] LI T, HOU J, YAN J L, et al. Chiplet heterogeneous integration technology-status and challenges[J]. Electronics, 2020, 9(4): 670.
[8] 林伟. 新一代层叠封装(PoP)的发展趋势及翘曲控制[J]. 中国集成电路, 2014: 46-52.
[9] 王阳元. 集成电路产业全书[M]. 北京: 电子工业出版社, 2018.
[10] Package-on-package (PoP) [EB/OL]. [2021-06-15]. https://c44f5d406df450f4a66b-1b94a87d576253d9446df0a9ca62e142.ssl.cf2.rackcdn.com/2019/08/PoP-TS114-CN.pdf.
[11] High performance BVA PoP package for mobile systems[EB/OL]. [2021-06-15]. https://www.invensas.com/wp-content/uploads/sites/9/2017/08/WP-000105RevA_InvensasBVAPoPTechnologyWhitePaper.pdf.
[12] Interposer PoP [EB/OL]. [2021-06-15]. https://c44f5d406df450f4a66b-1b94a87d576253d9446df0a9ca62e142.ssl.cf2.rackcdn.com/2019/08/Interposer-PoP-DS840.pdf.
[13] HSIEH M C. Advanced flip chip package on package technology for mobile applications[C]// 2016 17th International Conference on Electronic Packaging Technology (ICEPT). Aug. 16-19, 2016, Wuhan, China. IEEE, 2016.
[14] LAU J H, LI M, QINGQIAN M L, et al. Fan-out wafer-level packaging for heterogeneous integration[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2018, 8(9): 1544-1560.
[15] TSENG C F, LIU C S, WU C H, et al. InFO (wafer level integrated fan-out) technology[C]// 2016 IEEE 66th Electronic Components and Technology Conference (ECTC). May 31-June 3, 2016, Las Vegas, NV, USA. IEEE, 2016.
[16] YU D. A new integration technology platform: Integrated fan-out wafer-level-packaging for mobile applications[C]// 2015 Symposium on VLSI Technology (VLSI Technology). June 16-18, 2015, Kyoto, Japan. IEEE, 2015.
[17] HSIEH C C, WU C H, YU D. Analysis and comparison of thermal performance of advanced packaging technologies for state-of-the-art mobile applications[C]//2016 IEEE 66th Electronic Components and Technology Conference (ECTC), May 31-June 3, 2016, Las Vegas, NV, USA. IEEE, 2016: 1430-1438.
[18] CHUN S R, KUO T H, TSAI H Y, et al. InFO_SoW (system-on-wafer) for high performance computing[C]//2020 IEEE 70th Electronic Components and Technology Conference (ECTC). IEEE, 2020.
[19] Chip-on-chip (CoC) [EB/OL]. [2021-06-15]. https://c44f5d406df450f4a66b-1b94a87d576 253d9446df0a9ca62e142.ssl.cf2.rackcdn.com/2019/05/Chip-on-Chip-CoC-TS111-CN.pdf.
[20] HOU S Y, CHEN W C, HU C, et al. Wafer-level integration of an advanced logic-memory system through the second-generation CoWoS technology[J]. IEEE Transactions on Electron Devices, 2017, 64(10): 4071-4077.
[21] CHEN W C, HU C, TING K C, et al. Wafer level integration of an advanced logic-memory system through 2nd generation CoWoS technology[C]//2017 Symposium on VLSI Technology. June 5-8, 2017, Kyoto, Japan. IEEE, 2017.
[22] LIN M S, HUANG T H, TSAI C C, et al. A 7-nm 4-GHz Arm1-core-based CoWoS1 chiplet design for high-performance computing[J]. IEEE Journal of Solid-State Circuits, 2020, 55(4): 956-966.
[23] HOU S Y, HSIA H, TSAI C H, et al. Integrated deep trench capacitor in si interposer for CoWoS heterogeneous integration[C]//2019 IEEE International Electron Devices Meeting (IEDM). Dec. 7-11, 2019, San Francisco, CA, USA. IEEE, 2019.
[24] MAHAJAN R, QIAN Z G, VISWANATH R S. Embedded multi-die interconnect bridge-a localized, high-density multichip packaging interconnect[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2019, 9(10): 1952-1962.
[25] MAHAJAN R, SANKMAN R, PATEL N, et al. Embedded multi-die interconnect bridge (EMIB)-a high density, high bandwidth packaging interconnect[C]//2016 IEEE 66th Electronic Components and Technology Conference (ECTC). May 31-June 3, 2016, Las Vegas, NV, USA. IEEE, 2016: 557-565.
[26] VISWANATH R, CHANDRASEKHAR A, SRINIVASAN S, et al. Heterogeneous SoC integration with EMIB[C]//2018 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS). Dec. 16-18, 2018, Chandigarh, India. IEEE, 2018.
[27] PRASAD C, CHUGH S, GREVE H, et al. Silicon reliability characterization of Intel’s Foveros 3D integration technology for logic-on-logic die stacking[C]//2020 IEEE International Reliability Physics Symposium (IRPS). April 28-May 30, 2020, Dallas, TX, USA. IEEE, 2020.
[28] Foveros: 3D integration and the use of face-to-face chip stacking for logic devices[C]// 2019 IEEE International Electron Devices Meeting (IEDM). Dec. 7-11, 2019, San Francisco, CA, USA. IEEE, 2019.
[29] 郁元卫. 硅基异构三维集成技术研究进展[J]. 固体电子学研究与进展, 2021, 41(1): 1-9.
[30] ELSHERBINI A A, LIFF S M, SWAN J M. Heterogeneous integration using omni-directional interconnect packaging[C]//2019 IEEE International Electron Devices Meeting (IEDM). Dec. 7-11, 2019, San Francisco, CA, USA. IEEE, 2019.
[31] CHEN M F, CHEN F C, CHIOU W C, et al. System on integrated chips (SoICTM) for 3D heterogeneous integration[C]//2019 IEEE 69th Electronic Components and Technology Conference (ECTC). May 28-31, 2019, Las Vegas, NV, USA. IEEE, 2019: 594-599.
[32] HU C C, CHEN M F, CHIOU W C, et al. 3D Multi-chip integration with system on integrated chips (SoIC)[C]//2019 Symposium on VLSI Technology. June 9-14, 2019, Kyoto, Japan. IEEE, 2019.
[33] SHIVNARAINE R, IERSSEL M V, FARZAN K, et al. 11.2 A 26.5625-to-106.25 Gb/s XSR SerDes with 1.55pJ/b efficiency in 7nm CMOS[C]//2021 IEEE International Solid-State Circuits Conference (ISSCC). Feb. 13-22, 2021, San Francisco, CA, USA. IEEE, 2021: 182-184.
[34] TAJALLI A, HOFSTRA K L, HOLDEN B, et al. A 1.02-pJ/b 20.83-Gb/s/wire USR transceiver using CNRZ-5 in 16-nm FinFET[J]. IEEE Journal of Solid-State Circuits, 2020, 55(4): 1108-1123.
[35] GREENHILL D, HO R, LEWIS D, et al. A 14 nm 1GHz FPGA with 2.5D transceiver integration[C]//2017 IEEE International Solid-State Circuits Conference (ISSCC). Feb. 5-9, 2017, San Francisco, CA, USA. IEEE, 2017: 54-56.
[36] Intel. Overview of heterogeneous integration[EB/OL]. (2020-03-13)[2021-06-15]. https://www.intel.com/content/www/us/en/architecture-and-technology/programmable/heterogeneous-integration/overview.html.
[37] ARDALAN S, FARJADRAD R, KUEMERLE M, et al. Chiplet communication link: bunch of wires (BoW) [J]. IEEE MICRO, 2021, 41(1): 54-60.
[38] HUANG H H, TSAI C Y, TSAI J C, et al. From package to system thermal characterization and design of high power 2.5-D IC[C]//2019 International Conference on Electronics Packaging (ICEP), April. 17-20, 2019, Niigata, Japan. 2019: 36-41.
[39] HOU F Z，ZHANG H Y，HUANG D Z, et al. Microchannel thermal management system with two-phase flow for power electronics over 500 W/cm2 heat dissipation[J]. IEEE Transactions on Power Electronics, 2020, 35(10): 10592-10600.
[40] Heterogeneous integration roadmap 2019[EB/OL]. [2021-06-30]. https://eps.ieee.org/technology/heterogeneous-integration-roadmap/2019-edition.html.
[41] HUANG Y L, CHUNG C K, LIN C F, et al. LTD PKG. (Liquid thermal dissipation package) technology[C]//2019 14th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT). IEEE, 2019: 146-149.
[42] FLEMING E, KHOLMANOV I, SHI L. Enhanced specific surface area and thermal conductivity in ultrathin graphite foams grown by chemical vapor deposition on sintered nickel powder templates[J]. Carbon, 2018(136): 380-386.
[43] OPRINS H, BEYNE E. Thermal Analysis of a 3D flip-chip fan-out wafer level package (fcFOWLP) for high bandwidth 3D integration[C]//2019 18th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), May 28-31, 2019, Las Vegas, NV, USA. IEEE, 2019: 1234-1242.
[44] KIM S K, OH D S, HWANG S, et al. Electrical and thermal co-analysis of thermally efficient SiP for high performance applications[C]//2019 Electrical Design of Advanced Packaging and Systems (EDAPS), IEEE, 2019: 1-3.
[45] 李欣荣, 雷庭, 于迪, 等. 一种片上系统片外互连可靠性仿真技术研究[J]. 电子产品可靠性与环境试验, 2020, 38(2): 23-16.
[46] BORISKOV P, ERSHOVA N, PUTROLAYNEN V, et al. Temperature simulation of system-in-package produced with hybrid chip mounting technology[J]. International Conference on Information Processing and Control Engineering, 2019, 630:012013.
[47] 罗心月. 三维集成电路TSV阵列热特性研究[D]. 西安：西安电子科技大学, 2019.
[48] IWAI T, SAKAI T, MIZUTANI D, et al. Multilayer glass substrate with high density via structure for all inorganic multi-chip module[C]//2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019: 1952-1957.
[49] LEE J C, KIM J, KIM K W, et al. High bandwidth memory(HBM) with TSV technique[C]//Soc Design Conference. IEEE, 2016: 181-182.
[50] HBM2E opens the era of ultra-speed memory semiconductors[EB/OL]. (2019-10-25) [2021-06-15].https://news.skhynix.com/hbm2e-opens-the-era-of-ultra-speed-memory-semiconductors/.
[51] KOO B, LEE S M, CHAE K, et al. Industry-leading high bandwidth memory interface solutions for inference/AI[C]//Design Con, 2020.
[52] SABAN K. Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency[EB/OL]. (2012-11-11)[2021-06-15]. https://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf.
[53] WISSOLIK M, ZACHER D, TORZA A, et al. Virtex UltraScale + HBM FPGA : 革命性提升存储器的性能[EB/OL]. (2017-06-14)[2021-06-15]. https://china.xilinx.com/support/documentation/ white_papers/c_wp485-hbm.pdf.
[54] CHEN Y P, MAILLARD P, BARTON J, et al. Single-event evaluation of Xilinx 16 nm UltraScale+ high-bandwidth memory enabled FPGA[C]//2019 IEEE Radiation Effects Data Workshop, July 8-12, 2019, San Antonio, TX, USA. IEEE, 2019.
[55] Virtex UltraScale+ HBM FPGA[EB/OL]. [2021-06-15]. https://china.xilinx.com/ publications/product-briefs/virtex-ultrascale-plus-hbm-product-brief.pdf.
[56] DEO M. Enabling next-generation platforms using Intel’s 3D system-in-package technology[EB/OL]. [2021-06-15]. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01251-enabling-nextgen-with-3d-system-in-package.pdf?wapkw=Enabling%20Next-Generation%20Platforms%20Using%20Intel%E2%80%99s%203D%20System-in-Package%20Technology.
[57] VISWANATH R, CHANDRASEKHAR A, SRINIVASAN S, et al. Heterogeneous SoC integration with EMIB[C]//2018 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), Dec. 16-18, 2018, Chandigarh, India. IEEE, 2019.
[58] WADE M, ANDERSON E, ARDALAN S, et al. TeraPHY: A chiplet technology for low-power, high-bandwidth in-package optical I/O[J]. IEEE Micro, 2020, 40(2): 63-71.
[59] WADE M, ANDERSON E, ARDALAN S, et al. TeraPHY: A chiplet technology for low-power, high-bandwidth in-package optical I/O[C]//2019 IEEE Hot Chips 31 Symposium(HCS). Aug. 18-20, 2019, Cupertino, CA, USA. IEEE, 2019.
[60] KHUSHU S, GOMES W. Lakefield: Hybrid cores in 3D package[C]//2019 IEEE Hot Chips 31 Symposium (HCS), Aug. 18-20, 2019, Cupertino, CA, USA. 2019.
[61] Intel史上首款5核心揭秘：三个第1、待机功耗低至2.5 mW[EB/OL]. [2021-06-15]. https://baijiahao.baidu.com/s?id=1669207593232219243&wfr=spider&for=pc.
[62] Intel Kaby Lake G[EB/OL]. [2021-06-15]. https://en.wikichip.org/wiki/File:intel-radeon_emib_solution.svg.
[63] AMD EPYC? 7003 Series Processors[EB/OL]. [2021-06-15]. https://www.amd.com/en/processors/epyc-7003-series.
[64] EPYC-AMD[EB/OL]. [2021-06-15]. https://en.wikichip.org/wiki/amd/epyc.
[65] ODAJIMA T, KODAMA Y, TSUJI M, et al. Preliminary performance evaluation of the Fujitsu A64FX using HPC applications[C]//2020 IEEE International Conference on Cluster Computing (CLUSTER), Sept. 14-17, 2020,Kobe, Japan. 2020: 523-530.
[66] DANSKIN J, FOLEY D. Pascal GPU with NVLink[C]//2016 IEEE Hot Chips 28 Symposium (HCS), Aug. 21-23, 2016, Cupertino, CA, USA. 2016.
[67] FOLEY D, DANSKIN J. Ultra-performance Pascal GPU and NVLink interconnect[J]. IEEE Micro, 2017, 37(2): 7-17.
[68] LEE C C, HUNG C, CHEUNG C, et al. An overview of the development of a GPU with integrated HBM on silicon interposer[C]//2016 IEEE 66th Electronic Components and Technology Conference (ECTC). May 31-June 3, 2016, Las Vegas, NV, USA. 2016: 1439-1444.
[69] 曾燕萍, 张景辉, 王梦雅, 等. DDR3堆叠键合组件的信号完整性分析与优化[J]. 电子与封装, 2020, 20(12): 120201.

中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

面向信息处理应用的异构集成微系统综述^*

Overview of Heterogeneous IntegrationMicrosystem for Information Processing Applications

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 10

编辑推荐

Metrics

本文评价

[1]	张尚;张墅野;何鹏. 微混装焊料组织及力学性能研究进展[J]. 电子与封装, 2021, 21(8): 80101-.
[2]	周斌, 陈思, 王宏跃, 付志伟, 施宜军, 杨晓锋, 曲晨冰, 时林林. 异质异构微系统集成可靠性技术综述*[J]. 电子与封装, 2021, 21(10): 100110-.
[3]	张鹏, 孙晓冬, 朱家和, 王晶, 王大伟, 赵文生. 集成微系统多物理场耦合效应仿真关键技术综述^*[J]. 电子与封装, 2021, 21(10): 100104-.
[4]	张墅野, 李振锋, 何鹏. 微系统三维异质异构集成研究进展*[J]. 电子与封装, 2021, 21(10): 100106-.
[5]	张伟, 祝名, 李培蕾, 屈若媛, 姜贸公. 微系统发展趋势及宇航应用面临的技术挑战[J]. 电子与封装, 2021, 21(10): 100101-.
[6]	杨芳. 双路隔离CAN驱动器微系统[J]. 电子与封装, 2020, 20(9): 90404-.
[7]	吉勇，王成迁，李杨. 扇出型封装发展、挑战和机遇[J]. 电子与封装, 2020, 20(8): 80101-.
[8]	丁荣峥,蒋玉齐,吕栋,仝良玉. 陶瓷封装恒定加速度试验的分析与改进[J]. 电子与封装, 2020, 20(3): 30201-.
[9]	毛　臻，丁涛杰，杨　兵. 微系统技术助力数字助听器发展[J]. 电子与封装, 2019, 19(3): 44-48.
[10]	杨　芳，王良江. 数字信号处理微系统设计[J]. 电子与封装, 2016, 16(2): 19-22.