高可靠性的读写分离14T存储单元设计*

doi:10.16257/j.cnki.1681-1070.2022.0110

电子与封装 ›› 2022, Vol. 22 ›› Issue (1): 010303 . doi: 10.16257/j.cnki.1681-1070.2022.0110

高可靠性的读写分离14T存储单元设计*

张景波¹;朱亚男²;彭春雨²;赵强²

1. 工业和信息化部产业发展促进中心，北京　100084；2. 安徽大学集成电路学院，合肥　230601

收稿日期:2021-06-17 出版日期:2022-01-25 发布日期:2021-08-26
作者简介:张景波（1975—），男，山东省平度市，硕士，高级工程师，目前从事电子信息技术及其产业发展研究。

High Reliability Read-Write Separation14T Storage Cell Design

ZHANG Jingbo¹, ZHU Yanan², PENG Chunyu², ZHAO Qiang²

1. Industry Development andPromotion Center, Ministry of Industry and Information Technology of China,Beijing 100804, China; 2. School of Integrated Circuits,Anhui University, Hefei 230601, China

Received:2021-06-17 Online:2022-01-25 Published:2021-08-26

摘要/Abstract

摘要： 为了提高航空航天设备的可靠性和运行速度，提出了一种新型读写分离的14T SRAM单元。基于65 nm体硅CMOS工艺，对读写分离14T存储单元的性能进行仿真，并通过在关键节点注入相应的电流源模拟高能粒子轰击，分析了该单元抗SEU的能力。与传统6T相比，该单元写速度、读静态噪声容限和位线写裕度分别提升了约5.1%、20.7%和36.1%。写速度优于其他存储单元，读噪声容限优于6T单元和DICE单元，在具有较好的抗SEU能力的同时，提高了读写速度和读静态噪声容限。

关键词: 静态随机存储器, 高可靠性, 读写分离, 单粒子效应

Abstract: In order to improve the reliability and operating speed of aerospace equipment, a new type of 14T SRAM cell with read-write separation is proposed. Based on the 65 nm bulk silicon CMOS process, the performance of the proposed 14T memory cell is simulated; and, by injecting a corresponding current source into the key nodes to simulate high-energy particle struck, the anti-SEU capability of it is analyzed. Compared to the conventional 6T cell, the write speed, the read static noise margin and the bit line write margin are improved about 5.1%, 20.7% and 36.1%, respectively. The write speed is better than other memory cells, and the read noise tolerance is better than 6T cells and DICE cells. While having better anti-SEU capability, it also improves read and write speed and read static noise tolerance.

Key words: staticrandomaccessmemory, highreliability, read-writeseparation, singleeventeffect

中图分类号:

TN402

张景波;朱亚男;彭春雨;赵强. 高可靠性的读写分离14T存储单元设计*[J]. 电子与封装, 2022, 22(1): 010303 .

ZHANG Jingbo, ZHU Yanan, PENG Chunyu, ZHAO Qiang. High Reliability Read-Write Separation14T Storage Cell Design[J]. Electronics & Packaging, 2022, 22(1): 010303 .

参考文献

[1] NORMAND E, BAKER T J. Altitude and latitude variations in avionics SEU and atmospheric neutron flux[J]. IEEE Transactions on Nuclear Science, 1993, 40(6): 1484-1490.
[2] TABER A, NORMAND E. Single event upset in avionics[J]. IEEE Transactions on Nuclear Science, 1993, 40(2): 120-126.
[3] PENG C Y, HUANG J T, LIU C Y, et al. Radiation-hardened 14T SRAM bitcell with speed and power optimized for space application[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(2): 407-415.
[4] GUO J, ZHU L, LIU W Y, et al. Novel radiation-hardened-by-design (RHBD) 12T memory cell for aerospace applications in nanoscale CMOS technology[J]. IEEE Transactions on Very Large Scale Integration Systems, 2017, PP(5): 1-8.
[5] CALIN T, NICOLAIDIS M. Upset hardened memory design for submicron CMOS technology[J]. IEEE Transactions on Nuclear Science, 1996, 43(6): 2874-2878.
[6] IBE E, TANIGUCHI H, YAHAGI Y, et al. Impact of scaling on neutron-induced soft error in SRAMs from a 250 nm to a 22 nm design rule[J]. IEEE Transactions on Electron Devices, 2010, 57(7): 1527-1538.
[7] JAHINUZZAMAN S M, RENNIE D J, SACHDEV M. A soft error tolerant 10T SRAM bit-cell with differential read capability[J]. IEEE Transactions on Nuclear Science, 2009, 56(6): 3768-3773.
[8] DANG L, JIN S K, CHANG I J. We-quatro: radiation-hardened SRAM cell with parametric process variation tolerance[J]. IEEE Transactions on Nuclear Science, 2017(9): 1-1.
[9] GUO J, ZHU L, Sun Y, et al. Design of area-ef?cient and highly reliable RHBD 10T memory cell for aerospace applications[J]. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2018, 26(5): 991994.
[10] RAJAEI R, ASGARI B, TABANDEH M, et al. Design of robust SRAM cells against single-event multiple effects for nanometer technologies[J]. IEEE Transactions on Device and Materials Reliability, 2015, 15(3): 429-436.
[11] RAJAEI R, ASGARI B, TABANDEH M, et al. Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology[J]. Turkish Journal of Electrical Engineering and Computer Sciences, 2017, 25(2): 1-10.
[12] EFTAXIOPOULOS N, AXELOS N, PEKMESTZI K. Low latency radiation tolerant self-repair reconfigurable SRAM architecture[J]. Microelectronics Reliability, 2016, 56: 202-211.
[13] LI Y Q, WANG H B, LIU R, et al. A 65 nm temporally hardened flip-flop circuit[J]. IEEE Transactions on Nuclear Science, 2016, 63(6): 2934-2940.
[14] LE D, KANG M, Kim J, et al. Studying the variation effects of radiation hardened quatro SRAM bit-cell[J]. IEEE Transactions on Nuclear Science, 2016, 63(4): 2399-2401.
[15] WANG J, NALAM S, CALHOUN B H. Analyzing static and dynamic write margin for nanometer SRAMs[J]. IEEE, 2008: 129-134.
[16] 温亮．65 nm工艺高性能SRAM的研究与实现[D]．长沙：国防科学技术大学，2011.
[17] ZHANG H, HUI J, ASSIS T R, et al. Effects of threshold voltage variations on single-event upset response of sequential circuits at advanced technology nodes[J]. IEEE Transactions on Nuclear Science, 2017, 64(1): 457-463.
[18] PAL S, MOHAPATRA S, KI W H, et al. Design of soft-error-aware SRAM with multi-node upset recovery for aerospace applications[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2021, 68(6): 2470-2480.
[19] JIANG J, XU Y, ZHU W, et al. Quadruple cross-coupled latch-based 10T and 12T SRAM bit-cell designs for highly reliable terrestrial applications[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(3): 967-977.
[20] WU Z Y, CHEN S M. nMOS transistor location adjustment for N-hit single-event transient mitigation in 65-nm CMOS bulk technology[J]. IEEE Transactions on Nuclear Science, 2017.
[21] GUO J, XIAO L, WANG T, et al. Soft error hardened memory design for nanoscale complementary metal oxide semiconductor technology[J]. IEEE Transactions on Reliability, 2015, 64(2): 596-602.
[22] GUO J, XIAO L, MAO Z. Novel low-power and highly reliable radiation hardened memory cell for 65 nm CMOS technology[J]. IEEE Transactions on Circuits and Systems I Regular Papers, 2017, 61(7): 1994-2001.
[23] WANG H B, BI J S, LI M L, et al. An area efficient SEU-tolerant latch design[J]. IEEE Transactions on Nuclear Science, 2014, 61(6): 3660-3666.

中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

高可靠性的读写分离14T存储单元设计*

High Reliability Read-Write Separation14T Storage Cell Design

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 8

编辑推荐

Metrics

本文评价

[1]	谢文虎;郑天池;季振凯;杨茂林. 基于亿门级UltraScale+架构FPGA的单粒子效应测试方法[J]. 电子与封装, 2022, 22(7): 70202-.
[2]	高国平;赵维林. 片上SRAM物理不可克隆函数特性优化设计[J]. 电子与封装, 2022, 22(7): 70302-.
[3]	陈鑫;施聿哲;白雨鑫;陈凯;张智维;张颖. 单粒子翻转效应的FPGA模拟技术^*[J]. 电子与封装, 2021, 21(9): 90402-.
[4]	陈嘉鹏;何威;王威. 一种用于数字电路单粒子效应试验的系统设计[J]. 电子与封装, 2020, 20(11): 110304-.
[5]	王殿年;段嘉伟;刘艳明;王贺贺. 一种高可靠性环氧树脂组合物的制备[J]. 电子与封装, 2020, 20(10): 100201-.
[6]	金鑫，唐民，于庆奎，张洪伟，梅博，孙毅，唐路平. 粒子入射条件对28 nm SRAM 单元单粒子电荷共享效应影响的TCAD 仿真研究[J]. 电子与封装, 2019, 19(6): 32-40.
[7]	周昕杰，陈　瑶，花正勇，殷亚楠，郭　刚，蔡　丽. TCAD结合SPICE的单粒子效应仿真方法[J]. 电子与封装, 2019, 19(4): 32-35.
[8]	米　丹，左玲玲. 体硅CMOS集成电路抗辐射加固设计技术[J]. 电子与封装, 2016, 16(9): 40-43.