一种低功耗16 bit逐次逼近型ADC的设计

doi:10.16257/j.cnki.1681-1070.2023.0052

电子与封装 ›› 2023, Vol. 23 ›› Issue (5): 050305 . doi: 10.16257/j.cnki.1681-1070.2023.0052

一种低功耗16 bit逐次逼近型ADC的设计

王思远;李琨;叶明远;张涛

中国电子科技集团公司第五十八研究所，江苏无锡 214035

收稿日期:2022-11-07 出版日期:2023-05-23 发布日期:2023-05-23
作者简介:王思远（1994—），男，山西运城人，硕士，工程师，主要研究方向为ADC/DAC设计。

Design ofLow-Power Consumption 16bit SAR ADC

WANG Siyuan, LI Kun, YE Mingyuan, ZHANG Tao

China Electronics Technology GroupCorporation No.58 Research Institute, Wuxi214035,China

Received:2022-11-07 Online:2023-05-23 Published:2023-05-23

摘要/Abstract

摘要： 设计了一种低功耗的16 bit 1MSa/s SAR ADC。低功耗设计来源于电容阵列，其由3段子电容阵列构成，之间的桥接电容通过冗余电容和权重电容整数化。在电容阵列的切换过程中，通过将电容分裂来引入额外的参考电压。通过对量化噪声和热噪声的计算，可以精确地得出所需的电容数量为225个单位，相比于传统的电容阵列形式，可以节省99.93%的面积和99.5%的功耗。电路中使用一个2级预放大，并添加了具有自校零功能的动态锁存比较器，确保了高精度分辨率。在UMC55nm工艺下仿真，对512点的FFT仿真结果显示，ADC的整体信噪比（SNR）能够达到85.98dB，有效位数（ENOB）能够达到13.9bit，在电源电压为2.5V的情况下，平均功耗为5.05mW。

关键词: SARADC, 低功耗, 电容阵列, 自校零比较器

Abstract: A low-power 16bit 1MSa/s SAR ADC is designed. The low-power design is derived from a capacitor array consisting of a three-section sub-capacitor array, with the bridge capacitance between them integerised by redundant and weighted capacitors. An additional reference voltage is introduced by splitting the capacitors during the switching of the capacitor arrays. By calculating the quantization and thermal noise, the number of capacitors required can be accurately derived as 225 units, saving 99.93% area and 99.5% power consumption compared to the conventional capacitor array format. The circuit uses a two-stage pre-amplification and a self-zeroing dynamic latching comparator to ensure high precision resolution. Simulated in UMC 55 nm process, the FFT simulation results of 512 points show that the signal-to-noise ratio (SNR) of the overall ADC can reach 85.98 dB, the effective number of bits (ENOB) can reach 13.9 bit, and the average power consumption is 5.05 mW at a supply voltage of 2.5 V.

Key words: SAR ADC, low-power, capacitor array, self-calibration comparator

中图分类号:

TN402

王思远;李琨;叶明远;张涛. 一种低功耗16 bit逐次逼近型ADC的设计[J]. 电子与封装, 2023, 23(5): 050305 .

WANG Siyuan, LI Kun, YE Mingyuan, ZHANG Tao. Design ofLow-Power Consumption 16bit SAR ADC[J]. Electronics & Packaging, 2023, 23(5): 050305 .

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中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

一种低功耗16 bit逐次逼近型ADC的设计

Design ofLow-Power Consumption 16bit SAR ADC

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