中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

导航

电子与封装 ›› 2016, Vol. 16 ›› Issue (7): 44 -47. doi: 10.16257/j.cnki.1681-1070.2016.0087

• 微电子制造与可靠性 • 上一篇    

NAND Flash浮栅干法蚀刻工艺优化解决数据写入失效

陈 亮12,周朝锋2,李晓波2   

  1. 1.上海交通大学,上海200240;2.中芯国际上海集成电路股份有限公司,上海201507
  • 收稿日期:2016-03-16 出版日期:2016-07-20 发布日期:2016-07-20
  • 作者简介:陈 亮(1984—),男,安徽人,学士,研发工程师,毕业于同济大学,现就职于中芯国际集成电路制造有限公司,主要从事NAND Flash整合工艺开发。

NAND Flash Floating Gate Dry Etch Technology Optimization to Tackle Program Failure

CHEN Liang12,ZHOU Chaofeng2,LI Xiaobo2   

  1. 1.Shanghai Jiaotong University,Shanghai 200240,China;2.SMIC,Shanghai 201507,China
  • Received:2016-03-16 Online:2016-07-20 Published:2016-07-20

摘要: 随着移动终端的大量普及,存储器市场需求得到大幅度提升。NAND Flash以其大容量和体积小的优点,在目前的存储器市场占据着越来越重要的地位。产品良率是影响NAND Flash发展的一个重要因素。其中NAND Flash读写操作中的写入失效是良率损失最主要的原因。经分析,整合工艺的复杂性以及蚀刻制程工艺的局限性,浮栅和控制栅物理结构不完善会产生数据写入失效。着眼于对浮栅的干法蚀刻工艺进行改进,改善浮栅和控制栅物理结构,防止写入失效,从而得到最佳的良率。

关键词: NAND, Flash工艺制程, 浮栅, 控制栅, 干法蚀刻, 良率

Abstract: The memory demands have sharply increased due to the rapid development of smart devices. NAND Flash featuring large storage capacity and small volume has been playing an increasingly important role in memory market.However,yield is a key factor affecting NAND Flash development.During NAND flash operation,"Program"is the major reason causing yield loss.Analysis shows that imperfect Floating and Control Gate structure may lead to Program fail as a result of the limitation of Dry ETCH technology.The paper proposes an optimization method of Floating Gate Dry Etch technology to obtain better yield.

Key words: NAND, Flash technology, floating gate, control gate, dry ET, yield

中图分类号: