中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

导航

电子与封装 ›› 2018, Vol. 18 ›› Issue (3): 36 -39. doi: 10.16257/j.cnki.1681-1070.2018.0032

• 微电子制造与可靠性 • 上一篇    下一篇

多晶硅表面前处理对嵌入式闪存器件寄生电阻的减小

赵江1,2,顾培楼1,张雷1,陈珏1,奚晟蓉1   

  1. 1.上海华虹宏力半导体制造有限公司,上海 201206;2.上海交通大学电子信息与电气工程学院,上海 200240
  • 收稿日期:2017-11-02 出版日期:2018-03-20 发布日期:2018-03-20
  • 作者简介:赵江(1980—),吉林长春人,2006年6月毕业于吉林大学材料学院,材料物理与化学专业工学硕士,现就职于上海华虹宏力半导体制造有限公司,任高级工艺整合工程师,主要负责 0.13 μm embedded flash产品的生产与工艺优化工作。

Poly Surface Pre-clean for Parasitic Resistance Reduction in 0.13 μm Embedded Flash

ZHAO Jiang1,2,GU Peilou1,ZHANG Lei1,CHEN Jue1,XI Shengrong1   

  1. 1.Shanghai Huahong Grace Semiconductor Manufacturing Corporation,Shanghai 201203,China;2.School of Electronics Information and Electrical Engineering,Shanghai JiaoTong University,Shanghai 200240,China
  • Received:2017-11-02 Online:2018-03-20 Published:2018-03-20

摘要: 分析了一个发生在0.13 μm嵌入式闪存芯片中振荡器电路模块失效的案例。通过研究发现此失效与作为门极的多晶硅与后段金属互联线之间金属钨导线的接触电阻(晶体管寄生电阻)有关,而金属钨导线的接触电阻大小在很大程度上取决于多晶硅表面刻蚀前处理工艺。通过对多晶硅表面前处理工艺的优化实验,探讨了金属钨导线接触电阻减小的方法。

关键词: 0.13 μm嵌入式闪存, 钨导线, 接触电阻, 多晶硅表面刻蚀前处理

Abstract: In this article, we investigated an oscillator module test fail case of 0.13 μm embedded flash, which is caused by the high parasitic resistance in MOSFET device.Through electrical failure analysis and physical failure analysis we successfully observed the root cause of high parasitic resistance:it is due to gate poly surface pre-clean dry etch process is not enough to effectively remove the thermal oxide on gate poly surface and impact theWto gate poly contact resistance (RCGP).Based on the result of some experiments,we discuss the gate poly surface pre-clean dry etch process optimization method for RCGP reduction.

Key words: 0.13 μm embedded flash, W contact, parasitic resistance, poly surface pre-clean

中图分类号: