中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2018, Vol. 18 ›› Issue (8): 13 -16. doi: 10.16257/j.cnki.1681-1070.2018.0085

• 电路设计 • 上一篇    下一篇

12位单斜ADC的设计

陈科全,唐 鹤,郑炯卫,杨 磊,甄少伟,张 波   

  1. 电子科技大学,成都 610054
  • 出版日期:2018-08-20 发布日期:2018-08-20
  • 作者简介:陈科全(1993—),男,四川乐山人,现于电子科技大学攻读硕士学位,从事模数转换器设计研究。
  • 基金资助:
    “核心电子材料与器件协同创新中心”项目(ICEM2015-1001)

Design of 12-Bit Single-Slope ADC

CHEN Kequan, TANG He, ZHENG Jiongwei, YANG Lei, ZHEN Shaowei, ZHANG Bo   

  1. University of Electronic Science and Technology of China, Chengdu 610054, China
  • Online:2018-08-20 Published:2018-08-20

摘要: 介绍的单斜ADC(Analog-to-Digital Converter,ADC)应用于三维成像激光焦平面读出电路,将读出电路检测到的电压模拟信号转换为数字信号,便于后续的信号处理。根据焦平面阵列规格、对信号精度和速度的需求,选择采用单斜结构ADC,其中斜坡发生器和计数器两个模块可以所有列共用,每列只需一个比较器和寄存器。斜坡发生器采用分段电容阵列结构,大大减小了芯片面积。由于ADC精度较高,也对比较器进行了失调校准,同时提出了一种新结构,使得比较器输入范围扩大至轨到轨。提出的ADC基于0.18μm CMOS工艺进行设计,输入电压量化范围为1.1 V,量化精度为12位,转换速度为5 kHz。

关键词: ADC, 单斜, 分段电容, 失调校准, 轨到轨

Abstract: The single-slope ADC proposed in this paper is applied to the three-dimensional imaging laser focal plane readout circuit, which converts the voltage analog signal detected by the readout circuit into a digital signal for subsequent signal processing. According to the focal plane array specifications, the signal accuracy and speed requirements, we choose single-slope ADC. Because the ramp generator and counter can be shared by all columns, only one comparator and registers is needed per column. The ramp generator uses a split-capacitor array structure, which greatly reduces the chip area. We also calibrate the comparator offset due to high accuracy requirement of the ADC and propose a new structure that increases input range of comparator to rail-to-rail. The ADC proposed in this paper is based on 0.18μm CMOS process, the quantization precision is 12 bits with input voltage quantization range 1.1 V, and the conversion speed is 5 kHz.

Key words: ADC, single-slope, split-capacitor, offset calibration, rail-to-rail

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