基于开关电容放大器的低面积开销ADC*

doi:10.16257/j.cnki.1681-1070.2023.0105

电子与封装 ›› 2023, Vol. 23 ›› Issue (8): 080301 . doi: 10.16257/j.cnki.1681-1070.2023.0105

基于开关电容放大器的低面积开销ADC^*

黄合磊^1,2;佴宇飞^1,2;虞致国^1,2;顾晓峰^1,2

1.? 江南大学物联网技术应用教育部工程研究中心，江苏无锡 214122；2. 江南大学电子工程系，江苏无锡 214122

收稿日期:2023-02-22 出版日期:2023-08-24 发布日期:2023-07-06
作者简介:黄合磊（1998—），男，贵州盘州人，硕士研究生，主要研究方向为模拟集成电路设计。

Area-Efficient ADC Based on Switched-Capacitor Amplifier

HUANG Helei^1,2, NAI Yufei^1,2, YU Zhiguo^1,2, GU Xiaofeng^1,2

1. Engineering Research Center of Ministry ofEducation for IoT Technology Applications, Jiangnan University, Wuxi 214122,China;2. Department of Electronic Engineering, Jiangnan University,Wuxi 214122,China

Received:2023-02-22 Online:2023-08-24 Published:2023-07-06

摘要/Abstract

摘要： 针对模数转换器（ADC）在存内计算芯片中面积占比大的问题，提出了一种基于开关电容放大器的低面积开销ADC，包括一个全局数模转换器（GDAC）和基于开关电容放大器的局部列级ADC。整体电路采用单端逐次逼近型（SAR）ADC架构，利用开关电容放大器实现电压的逐次逼近，大幅度减少了单位电容数量，降低了局部列级ADC的整体面积开销；局部列级ADC共用由GDAC同步产生的参考电压，提高了ADC的整体面积效率。基于55 nm CMOS工艺设计了单列8位ADC，电源供电电压为1.2 V，输入电压范围为200~800 mV，在2.22 MSa/s的采样速率下，其功耗为144 μW，面积为792 μm²。仿真结果表明，ADC的有效位数为7.86 bit，无杂散动态范围为64.3 dB，品质因数（FoM）为987 pJ×μm²/conv。

关键词: 存内计算, 模数转换器, 全局数模转换器, 开关电容放大器, 低面积开销

Abstract: Aiming at the problem of the large area ratio of analog-to-digitalconverter (ADC) in the computing-in-memory chip, an area-efficient ADC based on the switched-capacitor amplifier is proposed, including a global digital-to-analog converter (GDAC) and local column parallel ADCs based on the switched-capacitor amplifier. The whole circuit adopts the single-ended successive-approximation register (SAR) ADC architecture and realizes successive approximation of voltage by the switched-capacitor amplifier, which significantly reduces the number of unit capacitors and the overall area cost of the local column parallel ADCs. The local column parallel ADCs share the reference voltage synchronously generated by the GDAC, which further improves the overall area efficiency of the ADC. A single-column 8-bit ADC is designed based on the 55 nm CMOS process. The power supply voltage is 1.2 V, the input voltage range of the ADC is 200-800 mV, the power consumption is 144 μW at the sampling rate of 2.22 MSa/s, and the area is 792 μm². The simulation results show that the effective number of bits is 7.86 bit, the spurious free dynamic range is 64.3 dB, and the figure of merit (FoM) is 987 pJ×μm²/conv.

Key words: computing-in-memory, analog-to-digital converter, global digital-to-analog converter, switched-capacitor amplifier, area-efficient

中图分类号:

TN402

黄合磊, 佴宇飞, 虞致国, 顾晓峰. 基于开关电容放大器的低面积开销ADC^*[J]. 电子与封装, 2023, 23(8): 080301 .

HUANG Helei, NAI Yufei, YU Zhiguo, GU Xiaofeng. Area-Efficient ADC Based on Switched-Capacitor Amplifier[J]. Electronics & Packaging, 2023, 23(8): 080301 .

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基于开关电容放大器的低面积开销ADC^*

Area-Efficient ADC Based on Switched-Capacitor Amplifier

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