中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2022, Vol. 22 ›› Issue (5): 050203 . doi: 10.16257/j.cnki.1681-1070.2022.0514

• 封装、组装与测试 • 上一篇    下一篇

3D堆叠封装热阻矩阵研究

黄卫1,2;蒋涵1,2;张振越1;蒋玉齐1;朱思雄1;杨中磊1   

  1. 1中国电子科技集团公司第五十八研究所,江苏 无锡 214072;2.中微高科电子有限公司,江苏 无锡 214035
  • 收稿日期:2021-11-18 出版日期:2022-05-26 发布日期:2022-01-05
  • 作者简介:黄  卫(1995—),男,安徽利辛人,硕士研究生,工程师,从事芯片封装的仿真设计、研发工作。

Research on Thermal Resistance Matrix of 3DStacked Package

HUANG Wei1,2, JIANG Han1,2, ZHANG Zhenyue1, JIANG Yuqi1, ZHU Sixiong1, YANG Zhonglei1   

  1. 1.ChinaElectronics Technology Group Corporation No.58 Research Institute, Wuxi 214072, China; 2.Wuxi Zhongwei High-Tech Electronics Co.,Wuxi 214035, China
  • Received:2021-11-18 Online:2022-05-26 Published:2022-01-05

摘要:

针对多芯片热阻矩阵的研究模型大多基于多芯片组件模型,多芯片为2D封装类型,而对3D芯片堆叠模型的热阻矩阵研究较少。以3D芯片堆叠模型为例,研究分析封装器件热阻扩散、热耦合的热阻矩阵。通过改变封装器件内部芯片功率大小,利用仿真模拟计算3D封装堆叠结构的芯片结温。将热阻矩阵计算的理论结果与仿真模拟得到的芯片结温进行对比分析,验证多层芯片堆叠封装体耦合热阻矩阵的准确性。

关键词: 热阻矩阵, 热耦合, 芯片堆叠, 芯片结温

Abstract: Most of the research models for the multi-chip thermal resistance matrix are based on the multi-chip component model, that is, the multi-chip is a 2D package type, and the thermal resistance matrix of the 3D chip stack model is less researched. This paper takes the 3D chip stacking model as an example to study and analyze the thermal resistance matrix of the thermal resistance diffusion and thermal coupling of the packaged device. By changing the power of the chip inside the packaged device, simulation is used to calculate the chip junction temperature of the 3D package stack structure. Finally, the theoretical results of the thermal resistance matrix calculation and the chip junction temperature obtained by the simulation are compared and analyzed to verify the accuracy of the coupled thermal resistance matrix of the multilayer chip stack package.

Key words: thermalresistancematrix, thermalcoupling, chipstacking, chipjunctiontemperature

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