芯片堆叠FPBGA产品翘曲度分析研究

doi:10.16257/j.cnki.1681-1070.2019.0036

电子与封装 ›› 2019, Vol. 19 ›› Issue (4): 01 -5. doi: 10.16257/j.cnki.1681-1070.2019.0036

• 封装、组装与测试 • 下一篇

芯片堆叠FPBGA产品翘曲度分析研究

杨建伟¹，饶锡林²

1.广东气派科技有限公司，广东东莞　523000； 2.深圳气派股份有限公司，广东深圳　518000

收稿日期:2018-12-10 出版日期:2019-04-20 发布日期:2019-01-16
作者简介:杨建伟（1981—），男，陕西安康人，本科，现任广东气派科技有限公司研发经理，从事半导体封装产品的研发工作。

The Warpage Study of Ultra-Thin Die Stack FPBGA Package

YANG Jianwei

1. Guangdong Chippacking technology Ltd., Dongguan 523000, China; 2. Shenzhen Chippacking technology Co. Ltd., Shenzhen 518000, China

Received:2018-12-10 Online:2019-04-20 Published:2019-01-16

摘要/Abstract

摘要： 翘曲问题广泛存在于基板类封装产品中，对于堆叠芯片FPBGA产品来说，控制产品的翘曲十分重要。在分析堆叠芯片FPBGA产品翘曲度与材料的热膨胀系数、体积、温度变化量关系的基础上，将翘曲仿真模拟和DOE相结合，确定出模塑料和芯片是影响翘曲度的主要因素，并找到最优化值。测量基板和产品的实际翘曲度，对比印证了仿真模拟的正确性，为设计开发类似产品时减小翘曲度提供了有效参考。

关键词: 芯片堆叠, 球栅阵列, 翘曲, 芯片裂损

Abstract: Warpage is very common issue in substrate package. It’s very critical for stack die FPBGA package as many issues cause by warpage. The paper is the study of warpage base on the real FPBGA package, analysis the warpage root cause theoretically, finds the main effects are material CTE, volume and temperature. The warpage simulation shows mold compound and die are major factors, finds the optimized factors to reduce warpage. Validates the simulation by shadow morie, help to reduce the warpage risk during similar package design and develop.

Key words: stack die, ball grid array, warpage, die crack

中图分类号:

TN405

杨建伟, 饶锡林. 芯片堆叠FPBGA产品翘曲度分析研究[J]. 电子与封装, 2019, 19(4): 01 -5.

YANG Jianwei. The Warpage Study of Ultra-Thin Die Stack FPBGA Package[J]. Electronics & Packaging, 2019, 19(4): 01 -5.

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中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

芯片堆叠FPBGA产品翘曲度分析研究

The Warpage Study of Ultra-Thin Die Stack FPBGA Package

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