中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2020, Vol. 20 ›› Issue (7): 070306 . doi: 10.16257/j.cnki.1681-1070.2020.0707

• 电路设计 • 上一篇    下一篇

用于1 GSample/s 14位ADC的运算跨导放大器

李泽宇1,2,郭轩2,武锦2,唐鹤1   

  1. 1. 电子科技大学,成都 610054;2. 中国科学院微电子研究所,北京 100029
  • 接受日期:2020-03-10 发布日期:2020-07-21
  • 作者简介:李泽宇(1994—),男,天津人,电子科技大学硕士,中国科学院微电子研究所联合培养生,现从事高速高精度数模混合电路方面的研究。

Operational Transconductance Amplifier Applied in 1 GSample/s 14 bit A/D Converter

LI Zeyu1,2, GUO Xuan2, WU Jin2, TANG He1   

  1. 1. University of Electronic Science and Technology of China, Chengdu 610054, China; 2. Institute of Microelectronics of the Chinese Academy of Sciences,Beijing 100029, China
  • Accepted:2020-03-10 Published:2020-07-21

摘要: 运算跨导放大器是流水线型ADC中乘法数模转换器(MDAC)模块的重要组成部分。设计了一种用于1 GSample/s 14位流水线型ADC的运算跨导放大器(OTA)。由于无线通信领域的应用需要,设计要求在1.8 V的电源电压下,实现1.6 V的差分输出并且能够满足ADC速度和精度要求的运算跨导放大器。采用增益自举电路的套筒式结构可使OTA同时具有高益带宽积(GBW)和高直流增益,并设计共源极放大器作为OTA的第二级实现较大输出摆幅。调零电阻和密勒补偿使OTA在较小功耗下获得合适的相位裕度,配合零极点分析可进一步优化OTA整体功耗。该运算放大器基于40 nm CMOS工艺实现。仿真表明,该运算跨导放大器的直流增益大于90 dB,GBW大于17 GHz,相位裕度大于80°,完全满足1 GSample/s 14位流水线型ADC的性能要求。

关键词: 运算跨导放大器, 乘法数模转换器, 增益自举电路, 零极点, 密勒补偿, 模数转换器

Abstract: Operational transconductance amplifier is an important part of multiplying digital to analog converter (MDAC) module in pipelined ADC. A kind of operational transconductance amplifier (OTA) for a 1 GSample/s 14 bit pipelined ADC is designed and implemented. Due to the application needs in the field of wireless communication, the operational transconductance, which can meet the requirements of ADC’s speed and accuracy needs to have differential output of 1.6 V implemented at the 1.8 V power supply. The telescopic structure with the gain bootstrapping circuit enables the OTA to have both high gain bandwidth product (GBW) and high DC gain, and the common source amplifier is designed as the second stage of the OTA to achieve large output swing. The zeroing resistor and miller compensation enable the OTA to obtain an appropriate phase margin with small power consumption, and the overall power consumption of the OTA can be further optimized with zero-pole analysis. The operational transconductance amplifier is implemented at 40 nm CMOS process. Simulation results show that the DC gain of the operational transconductance amplifier is more than 90 dB, the GBW is more than 17 GHz, and the phase margin is more than 80°, which fully meets the performance requirements of the 1 GSample/s 14 bit pipelined ADC.

Key words: operational transconductance amplifier, multiplying digital to analog converter, gain bootstrapping circuit, zero-pole, miller compensation, analog/digital converter

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