关键词: FinFET, SRAM型FPGA, PCIeGen3, 低功耗

Abstract: In the era of big data, there are more stringent requirements for high-speed buses with high bandwidth, low latency and high flexibility. The integration of peripheral component interconnect express (PCIe) with FPGA can meet the needs of emerging fields, but its performance of stability and low-power consumption at the high temperature and low temperature need to be explored.Focusing on the SRAM FPGA using 16 nm FinFET technology,a scheme of performance test, temperature rise test, and power consumption test at the high temperature and low temperature for high-speed communication of low-power PCIe generation 3 (Gen3) is built. The test results show that the communication between the tested circuit and the CPU is stable during the communication process, and the readrate and writerate can reach 3907 MB/s and 4430 MB/s, respectively, reaching 54.1% and 61.4% of the theoretical maximum bandwidth; the temperaturerise of the tested circuit is not significant, and the surface temperature of the circuit at roomtemperature is 18.4% lower than that of the control device; its power consumption at the high temperature of 125 ℃ is 41.9% lower than that of the control device. The circuit under this process can operate the PCIe Gen3 bus stably and achieve high-quality signal transmission in a low-power and low heating state.

Key words: FinFET, SRAM FPGA, PCIe Gen3, low-power consumption