电子与封装 ›› 2023, Vol. 23 ›› Issue (11): 110102 . doi: 10.16257/j.cnki.1681-1070.2023.0164
所属专题： ICTC 2023(集成电路测试大会)
• ICTC 2023(集成电路测试大会)专题 • 上一篇 下一篇
谢凌峰,武新郑,王建超
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作者简介:
XIE Lingfeng, WU Xinzheng, WANG Jianchao
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摘要： 千兆以太网收发器芯片是一种最高能支持1000 Mbit/s传输速率的高速接口芯片。介绍了该类芯片的功能、硬件配置，针对ATE测试机台设计了相应的外围电路，在ATE测试机台上进行了寄存器读写测试和回环测试，利用测试机抓取了千兆以太网芯片输出的数据，测试结果验证了千兆以太网收发器芯片的功能正确性。
关键词: 千兆以太网收发器芯片, 寄存器读写测试, 回环测试, ATE
Abstract: Gigabit Ethernet transceiver chip is a kind of high-speed interface chip, which supports up to1000 Mbit/s transmission rate.The functions and hardware configurations of this kind of chip are introduced. Corresponding peripheral circuits are designed for ATE test bench. Register read/write tests and loopback tests are completed on the ATE test bench. Output data of the Gigabit Ethernet chipis captured by the test bench, and test results verify the correctness of the functions of the Gigabit Ethernet transceiver chip.
Key words: Gigabit Ethernet transceiver chip, register read/write test, loopback test, ATE
中图分类号:
TN407
TP23
谢凌峰, 武新郑, 王建超. 基于ATE的千兆以太网收发器芯片测试方法[J]. 电子与封装, 2023, 23(11): 110102 .
XIE Lingfeng, WU Xinzheng, WANG Jianchao. Gigabit Ethernet Transceiver Chip Testing Method Based on ATE[J]. Electronics & Packaging, 2023, 23(11): 110102 .
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链接本文: http://ep.org.cn/CN/10.16257/j.cnki.1681-1070.2023.0164
http://ep.org.cn/CN/Y2023/V23/I11/110102
