三维集成堆叠结构的晶圆级翘曲仿真及应用

doi:10.16257/j.cnki.1681-1070.2024.0015

电子与封装 ›› 2024, Vol. 24 ›› Issue (4): 040201 . doi: 10.16257/j.cnki.1681-1070.2024.0015

• 封装、组装与测试 • 下一篇

三维集成堆叠结构的晶圆级翘曲仿真及应用

谭琳¹,王谦^1,2,郑凯³,周亦康³,蔡坚^1,2

1. 清华大学集成电路学院，北京? 100084；2. 清华大学北京信息科学与技术国家研究中心，北京? 100084；3. 北方集成电路技术创新中心北京有限公司，北京? 100176

收稿日期:2023-09-05 出版日期:2024-04-24 发布日期:2024-04-24
作者简介:谭琳（1975—），女，北京人，博士，高级工程师，主要研究方向为电子封装仿真与可靠性。

Wafer-Level Warpage Simulation and Applications of 3D Integrated Stacking Structure

TAN Lin¹, WANG Qian^1,2, ZHENG Kai³, ZHOU Yikang³, CAI Jian^1,2

1. School of Integrated Circuits,Tsinghua University, Beijing100084, China; 2. Beijing National Research Center for Information Science andTechnology, Tsinghua University, Beijing 100084, China; 3. SemiconductorTechnology Innovation CenterBeijingCorp., Beijing 100176, China

Received:2023-09-05 Online:2024-04-24 Published:2024-04-24

摘要/Abstract

摘要： 随着先进电子封装产品对低成本和高性能的需求不断提高，三维集成技术以其传输速度快、功耗低、封装尺寸小、系统集成度高等优势，逐渐成为一个主流研发方向。三维集成封装通常采用晶圆级制造技术，由于半导体制造工艺及三维结构设计的复杂性，加之晶圆尺寸增大、厚度减小等发展趋势，使得有效控制晶圆翘曲以保证产品良率和可靠性面临着更大挑战。针对12英寸晶圆的典型三维集成结构，采用有限元仿真分析方法，研究多层薄膜堆叠产生的晶圆翘曲。对临时键合、晶圆减薄、晶圆键合及解键合等不同晶圆制造工艺中的翘曲变化进行了模拟计算，并选取关键工艺及设计参数进行评估与优化。通过对比实际产品的测量结果验证了仿真模型的合理性，运用仿真方法为产品设计提供了参数选择的指导依据。

关键词: 电子封装, 三维集成, 晶圆级翘曲, 堆叠结构, 有限元仿真

Abstract: With the increasing demand for low-cost and high-performance of advanced electronic packaging products, 3D integration technology has gradually become a mainstream research and development direction due to its advantages of fast transmission speed, low power consumption, small packaging size and high system integration level. Usually, wafer level manufacturing technology is adopted in 3D integrated packaging. Due to the complexity of semiconductor manufacturing processes and 3D structural design, and coupled with the wafer size increase, thickness reduction and other development trends, the effective control of wafer warpage to ensure product yield and reliability is facing greater challenges. For typical 3D integrated structure of 12-inch wafer, finite element simulation analysis method is applied to study wafer warpage caused by multi-layered thin film stacking. Warpage variations in different wafer manufacturing processes, such as temporary bonding, wafer thinning, wafer bonding and debonding, are simulated. Key process and design parameters are selected for evaluation and optimization. Rationality of the simulation model is validated by comparison between measurement data of actual product and simulation results. The simulation method is used to provide guidance for parameter selection in product design.

Key words: electronic packaging, 3D integration, wafer-level warpage, stacking structure, finite element simulation

中图分类号:

TN305.94

谭琳,王谦,郑凯,周亦康,蔡坚. 三维集成堆叠结构的晶圆级翘曲仿真及应用[J]. 电子与封装, 2024, 24(4): 040201 .

TAN Lin, WANG Qian, ZHENG Kai, ZHOU Yikang, CAI Jian. Wafer-Level Warpage Simulation and Applications of 3D Integrated Stacking Structure[J]. Electronics & Packaging, 2024, 24(4): 040201 .

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三维集成堆叠结构的晶圆级翘曲仿真及应用

Wafer-Level Warpage Simulation and Applications of 3D Integrated Stacking Structure

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