中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2024, Vol. 24 ›› Issue (4): 040301 . doi: 10.16257/j.cnki.1681-1070.2024.0038

• 电路与系统 • 上一篇    下一篇

基于FPGA与AD/DA的JESD204B协议通信与控制模块设计

叶胜衣,宋刚杰,张诚   

  1. 中国电子科技集团公司第五十八研究所,江苏 无锡 ?214035
  • 收稿日期:2023-09-13 出版日期:2024-04-24 发布日期:2024-04-24
  • 作者简介:叶胜衣(1995—),男,江苏宿迁人,硕士,工程师,主要研究方向为FPGA可编程逻辑器件设计与仿真。

Design of JESD204B Protocol Communication and Control Module Based on FPGA and AD/DA

YE Shengyi, SONG Gangjie, ZHANG Cheng   

  1. China Electronics Technology Group CorporationNo.58 ResearchInstitute, Wuxi 214035, China
  • Received:2023-09-13 Online:2024-04-24 Published:2024-04-24

摘要: 为了完成高速射频信号的采集与发射,设计了基于FPGA、模数转换器AD9680与数模转换器AD9144电路的通信与控制模块。硬件设计主要包含前端设计、时钟设计、控制部分设计。软件部分则详细阐述了程序结构、模块设计以及程序执行流程。为兼容各种不同的AD/DA芯片且便于移植复用,所有数据处理以及寄存器配置都在FPGA的处理系统(PS)部分完成,在可编程逻辑(PL)部分完成与PS以及外设的数据交互与存储。该软件整体可视作一个软件封装IP。使用FPGA为主控芯片与AD/DA完成10 Gbit/s的线速率JESD204B链路通信,并以2 GSa/s的转换速率进行数据采集与发射,验证了设计的正确性。

关键词: 射频电路, 模数转换器, FPGA, JESD204B接口, DDR3

Abstract: In order to complete the acquisition and transmission of high-speed RF signals, a communication and control module based on FPGA, analog-to-digital converter AD9680, and digital-to-analog converter AD9144 circuit is designed. The hardware mainly includes front-end design, clock design, and control part design. The software section details the program structure, module design, and program execution process. In order to be compatible with various AD/DA chips and to facilitate transplantation and reuse, all data processing and register configuration are completed in the processing system (PS) section of FPGA, and data interaction and storage with the PS section and peripherals are completed in the programmable logic (PL) section. The whole software can be viewed as a software package IP. 10 Gbit/s line rate JESD204B link communication is accomplished between FPGA as the main control chip and AD/DA, and data acquisition and transmission are carried out at 2 GSa/s conversion rate, which verify the correctness of the design.

Key words: RF circuit, analog-to-digital converter, FPGA, JESD204B-interface, DDR3

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