中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2020, Vol. 20 ›› Issue (11): 110205 . doi: 10.16257/j.cnki.1681-1070.2020.1111

• 封装、组装与测试 • 上一篇    下一篇

一种基于ATE的SerDes物理层测试方法*

张凯虹,季伟伟,朱江   

  1. 中科芯集成电路有限公司,江苏 无锡 214035
  • 收稿日期:2020-06-03 发布日期:2020-07-23
  • 作者简介:张凯虹(1982—),女,山西文水人,硕士,研究方向是大规模集成电路的测试技术。

Test Method ofSerDes Physical layer based on ATE

ZHANG Kaihong, JI Weiwei, ZHU Jiang   

  1. China Key System& Integrated Circuit Co., Ltd., Wuxi 214035, China
  • Received:2020-06-03 Published:2020-07-23

摘要: 串行传输技术特别是串行解串器(SerDes)能提供比并行传输技术更高的带宽,被广泛应用于嵌入式高速传输领域。SerDes物理层的测试需要设备的带宽大于信号速率,测试指标高且测试端口接入会对信号产生影响。大多数厂商采用仪器仪表与评估板来评估待测器件(DUT)的方式效率低下,只适用于产品评估阶段。基于自动测试设备(ATE)与可测性设计(DFT)相结合的方式,采用高速串行接口源同步测试技术、测试通路校准与补偿等技术,对SerDes产品的功能、发送和接收端参数进行全面的测试,实现高速接口的快速准确测试,并可适用于其他同类SerDes芯片测试。

关键词: 串行解串器, 自动测试设备, 可测性设计, 源同步

Abstract: Serial transmission technology, especially serializer and deserializer (SerDes), which can provide higher bandwidth than parallel transmission technology, is widely used in the field of embedded high-speed transmission. In view of the bandwidth of the test equipment required for the SerDes physical layer test is larger than the signal rate, and the test index is high and the access of the test port will affect the signal, while most manufacturers use the instrument and evaluation board to evaluate the device under test (DUT), which is inefficient and only applicable to the problem of the evaluation stage. This paper is based on auto test equipment (ATE) and design for test (DFT), by using the key technologies such as source synchronous test technology of high-speed serial interface, calibration and compensation of test path, and also comprehensively tests the functions, sending and receiving parameters of SerDes products, so as to realize fast and accurate test of high-speed interface. In addition, it can be applied to other similar SerDes chip tests.

Key words: serializer anddeserializer, auto test equipment, design for test, source synchronous

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