关键词: TTL电平兼容, 高速CMOS端口电路, 传输延迟时间

Abstract: Based on the 0.8 μm CMOS process, a new transistor-transistor-logic (TTL) level compatible high-speed CMOS port circuit is designed, which not only realizes TTL-compatible input level, but also has the advantage of low transmission delay time. Circuit works at the temperature of－55-125 ℃. At 5 V operating voltage, the input flip level is 1.3 V, the transmission rise delay time is less than 1ns, and the falling delay time is less than 1 ns.

Key words: TTL level compatible, high-speed CMOS port circuit, transmission delay time