面向大规格矩阵协方差运算的高性能硬件加速器设计*

doi:10.16257/j.cnki.1681-1070.2024.0172

电子与封装 ›› 2024, Vol. 24 ›› Issue (12): 120306 . doi: 10.16257/j.cnki.1681-1070.2024.0172

面向大规格矩阵协方差运算的高性能硬件加速器设计^*

陈铠¹,刘传柱²,冯建哲¹,滕紫珩¹,李世平¹,傅玉祥²,李丽²,何国强¹

1.江苏华创微系统有限公司，南京? 211800；2. 南京大学电子科学与工程学院，南京?210023

收稿日期:2024-07-04 出版日期:2024-12-25 发布日期:2024-12-25
作者简介:陈铠（1979—），男，江苏南京人，硕士，高级工程师，主要研究方向为信号处理算法和人工智能算法高效能硬件实现、异构多核SoC芯片架构设计。

Design of High Performance Hardware Accelerator for Large-Scale Matrix Covariance Computation

CHEN Kai¹, LIU Chuanzhu², FENG Jianzhe¹, TENG Ziheng¹, LI Shiping¹, FU Yuxiang²,

1. Jiangsu Huachuang Microsystem Co., Ltd., Nanjing 211800, China; 2. School of Electronic Science and Engineering, Nanjing University, Nanjing 210023, China

Received:2024-07-04 Online:2024-12-25 Published:2024-12-25

摘要/Abstract

摘要： 随着雷达系统向多通道、高带宽方向发展，大规格矩阵带来的协方差运算实时性问题限制了空时二维自适应处理（STAP）技术在先进机载雷达平台上的应用。提出了一种高性能硬件加速器设计方法，旨在满足日益增长的大规格矩阵协方差处理需求，同时提高低功耗约束下的运算效率。加速器由运算部件、控制模块、存储模块和DMA控制器组成，通过对矩阵按列分段处理的方式，在硬件存储资源有限的条件下，支持最大256×8192的矩阵协方差运算。设计了下三角运算控制逻辑，降低了运算量，并提出了一套高并发乒乓存储、流水乘累加树处理机制，提高了处理效能。流片测试结果表明，该加速器处理大规格矩阵协方差运算时性能为算力接近的CPU核的70倍以上。

关键词: 协方差, 硬件加速器, 流水计算, 乘累加树, 乒乓存储

Abstract: With the development of radar systems toward multi-channel and high bandwidth, the real-time problem of covariance operation caused by large-scale matrix limits the application of space-time adaptive processing (STAP) technology in advanced airborne radar platforms. A high performance hardware accelerator design method is proposed to meet the increasing demand for large-scale matrix covariance processing and improve computational efficiency under low-power constraints. The accelerator is composed of computing unit, control module, storage module and DMA controller. It can support up to 256×8192 matrix covariance operation under the condition of limited hardware storage resources by processing the matrix in column segments. The control logic of the lower triangulation operation is designed to reduce the amount of computation, and a high-concurrency ping-pong storage mechanism along with a pipelined multiplication-accumulation tree processing method are proposed to enhance the processing efficiency. The tape-out test results show that the performance of the hardware accelerator in large-scale matrix covariance operations is more than 70 times that of a CPU core with similar computational capabilities.

Key words: covariance, hardware accelerator, pipeline computation, multiplication-accumulation tree, ping-pong storage

中图分类号:

TN492

陈铠, 刘传柱, 冯建哲, 滕紫珩, 李世平, 傅玉祥, 李丽, 何国强. 面向大规格矩阵协方差运算的高性能硬件加速器设计^*[J]. 电子与封装, 2024, 24(12): 120306 .

CHEN Kai, LIU Chuanzhu, FENG Jianzhe, TENG Ziheng, LI Shiping, FU Yuxiang, . Design of High Performance Hardware Accelerator for Large-Scale Matrix Covariance Computation[J]. Electronics & Packaging, 2024, 24(12): 120306 .

参考文献

[1] CUI W C, WANG T, WANG D G, et al. An improved iterative reweighted STAP algorithm for airborne radar[J]. Remote Sensing, 2022, 15(1): 130.
[2] CAO J X, WANG T, WANG D G. Beam-space post-Doppler reduced-dimension STAP based on sparse Bayesian learning[J]. Remote Sensing, 2024, 16(2): 307.
[3] 谢文冲, 段克清, 王永良. 机载雷达空时自适应处理技术研究综述[J]. 雷达学报, 2017, 6(6): 575-586.
[4] HUANG P H, ZOU Z H, XIA X G, et al. A novel dimension-reduced space-time adaptive processing algorithm for spaceborne multichannel surveillance radar systems based on spatial-temporal 2-D sliding window[J]. IEEE Transactions on Geoscience and Remote Sensing, 2022, 60: 1-21.
[5] GUERCI J R, RANGASWAMY M, BERGIN J S. Knowledge-aided space-time adaptive processing: application and advanced concepts[J]. IEEE Aerospace and Electronic Systems Magazine, 2019, 34(5): 54-66.
[6] SINGH S, SHRESTHA R. A new hardware-efficient and low sensing-time cooperative spectrum-sensor for high-throughput cognitive-radio network[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024, 71(1): 262-273.
[7] SONG D P, REN S W, ZHUO J, et al. FPGA implementation of covariance lattice LPC method using burg algorithm[C]//2017 9th International Conference on Advanced Infocomm Technology (ICAIT), Chengdu, China, 2017: 308-312.
[8] ZHOU Z, WANG H Y, YU G W. An improved MUSIC algorithm implemented with high-speed parallel optimization for FPGA[C]//2006 7th International Symposium on Antennas, Propagation & EM Theory, Guilin, China, 2006: 1-4.
[9] LI Z Y, WANG W J, JIANG R K, et al. Hardware acceleration of MUSIC algorithm for sparse arrays and uniform linear arrays[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(7): 2941-2954.
[10] BESIRIS D, TSAGARIS V, FRAGOULIS N, et al. An FPGA-based hardware implementation of configurable pixel-level color image fusion[J]. IEEE Transactions on Geoscience and Remote Sensing, 2012, 50(2): 362-373.
[11] KORAT U A, ALIMOHAMMAD A. A reconfigurable hardware architecture for principal component analysis[J]. Circuits, Systems, and Signal Processing, 2019, 38(5): 2097-2113.
[12] YAN J, HUANG Y Q, XU H T, et al. Hardware acceleration of MUSIC based DoA estimator in MUBTS[C]//The 8th European Conference on Antennas and Propagation (EuCAP 2014), The Hague, Netherlands, 2014: 2561-2565.
[13] HUANG K, SHA J, SHI W, et al. An efficient FPGA implementation for 2-D MUSIC algorithm[J]. Circuits, Systems, and Signal Processing, 2016, 35(5): 1795-1805.
[14] SCHELLHORN M, NOTNI G. Optimization of a principal component analysis implementation on field-programmable gate arrays (FPGA) for analysis of spectral images[C]//2018 Digital Image Computing: Techniques and Applications (DICTA), Canberra, Australia, 2018: 1-6.

中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

面向大规格矩阵协方差运算的高性能硬件加速器设计^*

Design of High Performance Hardware Accelerator for Large-Scale Matrix Covariance Computation

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 1

编辑推荐

Metrics

本文评价