关键词: DMA控制器, 低功耗设计, 暂停指令, 时钟门控技术, CDV, UVM

Abstract: By analyzing the working principle and main power sources of the direct memory access (DMA) controller, it is found that it still has the problem of high power consumption in the idle state. In order to solve the problem of power loss in the idle state and meet the pause requirement that may occur in the actual transmission process of the DMA controller, a design of pausable low-power DMA controller is proposed. The adaptive clock control mechanism is adopted. By adding the clock gating technology, the clock is dynamically adjusted according to the DMA data transmission requirement, and the power consumption of DMA engine is effectively reduced by 62%. For the pause requirement, a pausable control strategy is adopted. By adding a pausable instruction, the real-time pause and recovery of DMA transmission are realized, and the flexibility of the DMA controller is improved.

Key words: DMA controller, low-power design, pause instruction, clock gating technology, CDV, UVM