嵌入分段半超结的p-栅增强型垂直GaN基HFET*

doi:10.16257/j.cnki.1681-1070.2024.0096

电子与封装 ›› 2024, Vol. 24 ›› Issue (8): 080402 . doi: 10.16257/j.cnki.1681-1070.2024.0096

嵌入分段半超结的p-栅增强型垂直GaN基HFET^*

杨晨飞,韦文生,汪子盛,丁靖扬

温州大学电气与电子工程学院，浙江温州 325035

收稿日期:2024-01-21 出版日期:2024-09-11 发布日期:2024-09-11
作者简介:杨晨飞（1999—），男，浙江嘉兴人，硕士研究生，主要研究方向为宽禁带半导体功率器件。

p-Gate Enhanced Vertical GaN-Based HFET Embedded with Discrete Semi-Super-Junction

YANG Chenfei, WEI Wensheng, WANG Zisheng, DING Jingyang

Collegeof Electrical and Electronic Engineering, Wenzhou University,Wenzhou 325035, China

Received:2024-01-21 Online:2024-09-11 Published:2024-09-11

摘要/Abstract

摘要： 元胞面积相同的增强型垂直GaN/AlGaN异质结场效应管比横向HFET能承受更高的电压和更大的电流，适用于大功率领域，但在耐压时漂移区场强峰值高而容易提前击穿。提出了一种嵌入分段半超结的增强型垂直HFET，利用p型掺杂GaN栅和p⁺型掺杂GaN电流阻挡层抬高GaN/AlGaN异质结导带至费米能级之上，在栅压为0时夹断异质结的2DEG沟道，实现增强功能；在漂移区两侧插入2段p-GaN柱，形成p/n/p型离散半超结，改善电场均匀性。采用Silvaco TCAD软件模拟了Al组份、CBL浓度、p-GaN柱的宽度和厚度等参数对器件性能的影响。结果表明，相比于包含普通半超结的HFET，本器件的击穿电压提升了8.67%，静态品质因数提升了11.25%，导通延时缩短了16.38%，关断延时缩短了3.80%，可为设计高性能HFET提供新思路。

关键词: 增强型垂直HFET, 分段半超结, GaN/AlGaN异质结

Abstract: The enhanced vertical GaN/AlGaN hetero-junction field effect transistor (HFET) can withstand higher voltages and higher currents than the lateral HFET with the same cell area, which is more suitable for high-power electronics. However, it may suffer easily from premature breakdown during the withstand voltage due to strong electric field peak occurring in the drift region. An enhanced vertical HFET embedded with discrete semi-super-junction is proposed, where the p-type doped GaN gate layer and p⁺-type doped GaN current barrier layer are used to elevate the GaN/AlGaN hetero-junction conduction band above the Fermi energy level for clamping-off the 2DEG channel at the hetero-junction when the gate voltage is zero, and to realize the enhancement function. Two separate p-type doped GaN pillars are inserted at both sides of the drift region (DR) to form p/n/p-type discrete semi-super-junction for improving the electric field uniformity. The influences of Al component, CBL concentration, width and thickness of the p-GaN pillar on the device performance are simulated by the Silvaco TCAD software. The results indicate that compared with the HFET included a common semi-super-junction, the breakdown voltage of the proposed device increases by 8.67%, the static figure of merit lifts by 11.25%, the turn-on delay time shortens by 16.38%, and the turn-off delay time curtails by 3.80%, which can provide a new idea for designing high-performance HFET.

Key words: enhanced vertical HFET, discrete semi-super-junction, GaN/AlGaN heterojunction

中图分类号:

TN323⁺.4

杨晨飞,韦文生,汪子盛,丁靖扬. 嵌入分段半超结的p-栅增强型垂直GaN基HFET^*[J]. 电子与封装, 2024, 24(8): 080402 .

YANG Chenfei, WEI Wensheng, WANG Zisheng, DING Jingyang. p-Gate Enhanced Vertical GaN-Based HFET Embedded with Discrete Semi-Super-Junction[J]. Electronics & Packaging, 2024, 24(8): 080402 .

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中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

嵌入分段半超结的p-栅增强型垂直GaN基HFET^*

p-Gate Enhanced Vertical GaN-Based HFET Embedded with Discrete Semi-Super-Junction

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