关键词: FPGA时序库, FPGA架构, 时钟测试

Abstract: As a key part of the field programmable gate array (FPGA) circuit, the clock currently has problems such as large errors and difficulties in building test cases in the test methods. Based on the existing FPGA architecture, a new test method that converts the clock delay of the part to be tested into the duty cycle of the output clock is proposed. The research results show that the new test method successfully shields the error interference brought by external test devices, reduces the difficulty of building test cases, and greatly expands the test range of the clock delay in the chip. And it provides a strong guarantee for building an accurate timing library for FPGA.

Key words: FPGA timing library, FPGA architecture, clock test