中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2021, Vol. 21 ›› Issue (8): 080404 . doi: 10.16257/j.cnki.1681-1070.2021.0813

• 微电子制造与可靠性 • 上一篇    下一篇

集成电路检验/失效分析过程芯片去层制备方法

汪小青;虞勇坚;马勇;刘晓晔;吕栋   

  1. 中科芯集成电路有限公司,江苏 无锡 214035
  • 收稿日期:2020-12-10 出版日期:2021-08-11 发布日期:2021-03-15
  • 作者简介:汪小青(1989—),女,江苏盐城人,本科,主要从事集成电路失效分析工作。

Discussion on Chip De-layeringMethod in the Process of Integration Circuit Inspection and Analysis

WANG Xiaoqing, YU Yongjian, MA Yong, LIU Xiaoye, LYU Dong   

  1. China Key System & Integrated Circuit Co., Ltd., Wuxi 214035, China
  • Received:2020-12-10 Online:2021-08-11 Published:2021-03-15

摘要: 集成电路检验和失效分析相关标准中提出了芯片去层制备的要求,但因未提供相应的操作方法而缺乏可操作性。去层制备方法与芯片的物理层次结构和材料紧密相关,探讨了离子刻蚀法、机械研磨法、化学腐蚀法等去层制备方法与芯片物理层次、材料的适用性,选用实际芯片完成玻璃钝化层、介质层和金属化层的制备和去除,获得了可以满足检验和分析要求的物理层次。提出的芯片去层制备方法可以为相应标准提供补充,使其具有可操作性,为检测机构和用户单位的检验和分析过程提供了参考。

关键词: 芯片, 失效分析, 去层

Abstract: The requirements of chip preparation are put forward in the standards of IC inspection and failure analysis, but the operability is lacking because the corresponding operation methods are not provided. This paper analyzes the close relationship between de-layering process and physical structure as well as materials of integrated circuit, meanwhile discusses the applicability of preparation methods through reactive ion etching, mechanical grinding and chemical corrosion. Afterwards, practical cases are carried out to verify the preparation and removal of passivation layer, dielectric layer and metallization layer. Results show that various physical layers are obtained within the requirements of inspection and analysis. The proposed chip de-layering preparation method can supplement the corresponding standards, provide reference for testing institutions and users in the process of inspection and analysis, and make it operable.

Key words: chip, failureanalysis, de-layer

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