中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2020, Vol. 20 ›› Issue (2): 020301 . doi: 10.16257/j.cnki.1681-1070.2020.0207

• 电路设计 • 上一篇    下一篇

一种ECC校验算法的设计与实现

刘梦影,蔡阳阳   

  1. 中科芯集成电路有限公司,江苏 无锡 214072
  • 收稿日期:2019-10-12 出版日期:2020-02-24 发布日期:2020-02-24
  • 作者简介:刘梦影(1991—),女,江苏江阴人,硕士,2016年毕业于南京航空航天大学控制工程专业,工程师,现从事IC设计工作。

Design and Implementation of ECC Checking Algorithm

LIU Mengying, CAI Yangyang   

  1. China Key System& Integrated Circuit Co., Ltd., Wuxi 214072, China
  • Received:2019-10-12 Online:2020-02-24 Published:2020-02-24

摘要: 电可擦除可编程存储器(EEPROM)由于工艺结构的局限性而导致数据在存储过程中存在小概率的位反转问题。为解决该现象,设计了基于汉明码的纠错码(ECC)校验系统。结合EEPROM的结构特点和数据存储模式,该系统包含ECC校验码计算模块和数据检错纠错模块,每32 bit 数据生成6 bit ECC校验码,具有1 bit/32 bit的纠错力。采用硬件描述语言Verilog HDL设计并实现了该ECC验证系统,并将其应用于基于串行外设接口(SPI)的EEPROM。仿真结果表明ECC验证系统可以保证数据的正确率,提高存储系统的可靠性。

关键词: 电可擦除可编程存储器, 纠错码, 串行外设接口

Abstract: To solve the problem of bit-flipping of data resulting from the limitation of the process structure of electrically erasable programmable read only memory (EEPROM), an error correction check (ECC) checking system based on Hamming code is designed. Taking the structural characteristics and data storage of EEPROM into consideration, the system is divided into ECC calculation module and check and correction module which can achieve 1 bit/32 bit error correction capability by generating 6 bits of ECC code from per 32 bits of original data. This ECC checking system is designed and implemented by using Verilog HDL, which is applied to an EEPROM memory compatible with serial peripheral interface (SPI). The simulation result indicates that this ECC checking system can not only ensure the accuracy of transform, but also enhance the reliability of memory system.

Key words: electrically erasable programmable read only memory, error correction check, serial peripheral interface

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