关键词: 多晶硅发射极晶体管, 放大系数, 界面氧化层, 退火

Abstract: In this paper，the technological process of NPN type ploysilicon emitter transistor is analyzed, and a strict control scheme is proposed for the ploysilicon deposition process, so that the thickness of the oxide layer at the multi-grain interface is stable at 0.6-0.8nm. At the same time, the annealing process of base area and transmitting area was optimized, which improved the inter-chip uniformity of the amplification coefficient of the ploysilicon emitter transistor from 30% to 20%, and the uniformity between the chips increased from 12% to 9%, which significantly improved the product yield.

Key words: ploysiliconemittertransistor, amplificationcoefficient, interfaceoxidelayer, annealing