[1] CHANG M F, ROYCHOWDHURY V P, ZHANG L Y, et al. RF/wireless interconnect for inter- and intra-chip communications[J]. Proceedings of the IEEE, 2001, 89(4): 456-466. [2] FAN J, YE X N, KIM J, et al. Signal integrity design for high-speed digital circuits: Progress and directions[J]. IEEE Transactions on Electromagnetic Compatibility, 2010, 52(2): 392-400. [3] ROSKER M J. Technologies for next generation T/R modules[C]// 2007 IEEE Radar Conference, Waltham, MA, USA, 2007: 944-947. [4] 徐锐敏, 陈志凯, 赵伟. 微波集成电路的发展趋势[J]. 微波学报, 2013, 29(5): 55-60. [5] DONNAY S, PIETERS P, VAESEN K, et al. Chip-package codesign of a low-power 5-GHz RF front end[J]. Proceedings of the IEEE, 2000, 88(10): 1583-1597. [6] TIAN W C, LI P, YUAN L X. Research and analysis of MEMS switches in different frequency bands[J]. Micromachines, 2018, 9(4): 185. [7] CARCHON G, VAESEN K, BREBELS S, et al. Multilayer thin-film MCM-D for the integration of high-performance RF and microwave circuits[J]. IEEE Transactions on Components and Packaging Technologies, 2001, 24(3): 510-519. [8] SHAM M L, CHEN Y C, LEUNG L W, et al. Challenges and opportunities in system-in-package (SiP) business[C]// 2006 7th International Conference on Electronic Packaging Technology, Shanghai, 2006: 26-30. [9] MAURELLI A, BELOT D, CAMPARDO G. SoC and SiP, the Yin and Yang of the Tao for the new electronic era[J]. Proceedings of the IEEE, 2009, 97(1): 9-17. [10] WANG H Y, MA J S, YANG Y D, et al. A review of system-in-package technologies: application and reliability of advanced packaging[J]. Micromachines, 2023, 14(6): 1149. [11] BRAUN T, BECKER K F, KOCH M, et al. Flip chip molding-recent progress in flip chip encapsulation[C]// 2002 Proceedings. 8th International Advanced Packaging Materials Symposium, Stone Mountain, GA, USA, 2002. [12] 徐榕青, 卢茜, 张剑, 等. 用于RF系统级封装的微凸点技术[J]. 电子工艺技术, 2020, 41(5): 249-251. [13] BRAUN T, BECKER K F, KOCH M, et al. Flip chip molding-highly reliable flip chip encapsulation[C]// IEEE 52nd Electronic Components and Technology Conference, San Diego, CA, USA, 2002. [14] Yole Intelligence.Yole Group-Follow the Latest Trend News in the Semiconductor Industry[EB/OL] (2021-7-1)[2023-8-30].https://www.yolegroup.com/product/report/system-in-package-technology-and-market-trends-2021. [15] 漆学利. PBGA板级组件焊点随机振动可靠性分析与研究[D]. 广州: 华南理工大学, 2011. [16] 别晓锐, 秦飞. 电子封装焊点的可靠性及其热疲劳寿命预测模型[C]// 北京力学会第十九届学术年会, 北京, 2013:162-163. [17] LEE W W, NGUYEN L T, SELVADURAY G S. Solder joint fatigue models: review and applicability to chip scale packages[J]. Microelectronics Reliability, 2000, 40(2): 231-244. [18] LALL P, GUPTE S, CHOUDHARY P, et al. Solder joint reliability in electronics under shock and vibration using explicit finite-element submodeling[J]. IEEE Transactions on Electronics Packaging Manufacturing, 2007, 30(1): 74-83. [19] WANG J H, XUE S B, ZHANG P, et al. The reliability of lead-free solder joint subjected to special environment: A review[J]. Journal of Materials Science: Materials in Electronics, 2019, 30(10): 9065-9086. [20] LAI Y S, CHIU Y T, CHEN J. Electromigration reliability and morphologies of Cu pillar flip-chip solder joints with Cu substrate pad metallization[J]. Journal of Electronic Materials, 2008, 37(10): 1624-1630. [21] YU B Y, GAO Y S. Multi-physics fields simulations and optimization of solder joints in advanced electronic packaging[J]. Chips, 2022, 1(3): 191-209. [22] GUO H, ZHANG L, YIN L M. Phase field study on the effect of roughness on interfacial intermetallic compounds of micro-solder joints under multifield coupling[J]. Microelectronics Reliability, 2022, 137: 114792. [23] YAMANAKA K, OOYOSHI T, NEJIME T. Temperature measurement at flip chip solder joint during electromigration test[J]. Journal of Materials Science: Materials in Electronics, 2010, 21(1): 53-57. [24] CONSTABLE J H, SAHAY C. Electrical resistance as an indicator of fatigue[J]. IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1992, 15(6): 1138-1145. [25] CONSTABLE J H. Use of interconnect resistance as a reliability tool[C]// 1994 Proceedings. 44th Electronic Components and Technology Conference, Washington, DC, USA, 1994. [26] CONSTABLE J H, LIZZUL C. An investigation of solder joint fatigue using electrical resistance spectroscopy[J]. IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, 1995, 18(1): 142-152. [27] QI H Y, VICHARE N M, AZARIAN M H, et al. Analysis of solder joint failure criteria and measurement techniques in the qualification of electronic products[J]. IEEE Transactions on Components and Packaging Technologies, 2008, 31(2): 469-477. [28] CAERS J F J, WONG E H, SEAH S K W, et al. A study of crack propagation in Pb-free solder joints under drop impact[C]// 2008 58th Electronic Components and Technology Conference, Lake Buena Vista, FL, USA, 2008. [29] KWON D, AZARIAN M H, PECHT M G. Detection of solder joint degradation using RF impedance analysis[C]// 2008 58th Electronic Components and Technology Conference, Lake Buena Vista, FL, USA, 2008. [30] KANG T Y, SEO D, PARK Y, et al. Early detection and instantaneous cause analysis of defects in interconnects by machine learning (ranking-CNN) of scattering parameter patterns[J]. International Symposium on Microelectronics, 2019(1): 000289-000294. [31] GILS M A J V, DRIEL W D V, ZHANG G Q, et al. Virtual qualification of moisture induced failures of advanced packages[J]. Microelectronics Reliability, 2007, 47(2/3): 273-279. [32] MANUKOVSKY A, SHLEPNEV Y. Measurement-assisted extraction of PCB interconnect model parameters with fabrication variations[C]// 2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Montreal, QC, Canada, 2019: 1-3. [33] PAN S J, KAPOOR R, SUN A Y S, et al. A comparison of electrical performance between a wire bonded and a flip chip CSP package[C]// IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, San Jose, CA, USA, 2003:125-130. [34] 周江, 张先荣, 钟丽. 基于BGA互联的毫米波模块三维集成设计[J]. 电讯技术, 2019, 59(6): 724-728. [35] LEE M, CHO J, KIM J, et al. Temperature-dependent through-silicon via (TSV) model and noise coupling[C]// 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, San Jose, CA, USA, 2011: 247-250. [36] FAZLULLAH F, KAISER M S, AHMED S R. A comparative electro-mechanical characterization of tin-lead solder with equal proportion[C]// 2020 International Conference on Computer, Electrical & Communication Engineering (ICCECE), Kolkata, India, 2020: 1-6. [37] SHARMA A, YU H, CHO I S, et al. ZrO2 nanoparticle embedded low silver lead free solder alloy for modern electronic devices[J]. Electronic Materials Letters, 2019, 15(1): 27-35. [38] HAMMAD A E, RAGAB M. Achieving microstructure refinement and superior mechanical performance of Sn-2.0Ag-0.5Cu-2.0Zn (SACZ) solder alloy with rotary magnetic field[J]. Microelectronics and Reliability, 2020, 113: 113932. [39] LONG X, SU T X, LU C H, et al. An insight into dynamic properties of SAC305 lead-free solder under high strain rates and high temperatures[J]. International Journal of Impact Engineering, 2023, 175: 104542. [40] SHIH T I, LIN Y C, DUH J G, et al. Electrical characteristics for Sn-Ag-Cu solder bump with Ti/Ni/Cu under-bump metallization after temperature cycling tests[J]. Journal of Electronic Materials, 2006, 35(10): 1773-1780. [41] AZARIAN M H, LANDO E, PECHT M. An analytical model of the RF impedance change due to solder joint cracking[C]// 2011 IEEE 15th Workshop on Signal Propagation on Interconnects (SPI), Naples, Italy, 2011: 89-92. [42] LIU Z W, SUN Y F. A solder joint crack--characteristic impedance model based on transmission line theory[C]// 2014 10th International Conference on Reliability, Maintainability and Safety (ICRMS), Guangzhou, China, 2014: 237-241. [43] LIU D S, NI C Y. A study on the electrical resistance of solder joint interconnections[J]. Microelectronic Engineering, 2002, 63(4): 363-372. [44] HEINRICH W, HOSSAIN M, SINHA S, et al. Connecting chips with more than 100 GHz bandwidth[J]. IEEE Journal of Microwaves, 2021, 1(1): 364-373. [45] 黄春跃, 黄根信, 梁颖, 等. 面向完整传输路径的BGA焊点信号完整性分析及优化[J]. 焊接学报, 2019, 40(3): 25-31. [46] 郭广阔. 系统级封装BGA焊点及埋入式电容信号完整性研究[D]. 桂林: 桂林电子科技大学, 2014. [47] CHANDRAKAR S, GUPTA D, MAJUMDER M K, et al. Performance analysis of bump in tapered TSV: Impact on crosstalk and power loss[J]. IEEE Open Journal of Nanotechnology, 2022, 3: 227-235. [48] CHANDRAKAR S, DAS K K, GUPTA D, et al. Signal integrity and power loss analysis for different bump structures in cylindrical TSV[C]// International Symposium on VLSI Design and Test. Cham: Springer Nature Switzerland, 2022: 358-372. |