一种高PSRR低压差线性稳压器电路*

doi:10.16257/j.cnki.1681-1070.2024.0046

电子与封装 ›› 2024, Vol. 24 ›› Issue (4): 040303 . doi: 10.16257/j.cnki.1681-1070.2024.0046

一种高PSRR低压差线性稳压器电路^*

黄立朝¹,丁宁¹,沈泊言¹,余文中^2,3,4,樊华^2,3,4,曾泳钦⁴,冯全源⁵

1. 中国电子科技集团公司第五十八研究所，江苏无锡? 214035；2. 电子科技大学重庆微电子产业技术研究院，重庆 401331；3. 电子科技大学广东电子信息工程研究院, 广东东莞 ?523808；4. 电子科技大学集成电路科学与工程学院示范性微电子学院，成都? 611731；5. 西南交通大学信息科学与技术学院，成都? 611756

收稿日期:2023-10-16 出版日期:2024-04-24 发布日期:2024-04-24
作者简介:黄立朝 (1977—)，男，陕西渭南人，硕士，高级工程师，现从事模拟集成电路设计研发工作，主要研究方向为精密运算放大器、温度传感器等；樊华(1981—)，女，四川资阳人，博士，教授/博士生导师，现从事模拟集成电路设计研发工作，主要研究方向为高精度数据转换器、传感器等。

High PSRR Low Dropout Linear Regulator

HUANG Lichao¹, DING Ning¹, SHEN Boyan¹, YU Wenzhong^2,3,4, FAN Hua^2,3,4, ZENG Yongqin⁴, FENG Quanyuan⁵

1. China Electronics Technology Group CorporationNo.58 Research Institute, Wuxi 214035, China; 2. ChongqingInstitute of Microelectronics Industry Technology, UESTC, Chongqing 401331, ?China; 3. GuangdongInstitute of Electronic and Information Engineering, UESTC,Dongguan 523808, China; 4. School ofIntegrated Circuit Science and Engineering Exemplary School of Microelectronics, UESTC, Chengdu 611731, China; 5. The School of Information Science & Technology, SouthwestJiaotong University, Chengdu611756, China

Received:2023-10-16 Online:2024-04-24 Published:2024-04-24

摘要/Abstract

摘要： 通过对低压差线性稳压器（LDO）的电源抑制比（PSRR）进行理论分析得出，功率管栅极电压与LDO输入电压的小信号比值越接近1，PSRR就越高。基于此理论，在传统LDO的基础上增加了1种新结构，将二极管连接形式的MOS管与共源共栅结构串联，使功率管栅极电压与LDO输入电压的小信号比值接近1。随后，对该结构进行了理论分析，分析结果表明相比其他的PSRR提升技术，具有该结构的LDO其PSRR不会随着负载电流的增加而发生较大变化。LDO改进前和改进后PSRR的绝对值分别为65 dB和76 dB；改进后的结构在不同的负载电流下均具有较高的PSRR。相比体驱动前馈以及增加电荷泵将电源回路与LDO主体电路隔离等PSRR提升技术，该方法仅在传统LDO上增加了3个MOS管，减小了电路的功耗和面积。

关键词: 模拟集成电路, 电源管理, 模拟LDO, 电源抑制比

Abstract: The power supply rejection ratio (PSRR) of low dropout linear regulator (LDO) is theoretically analyzed, and it is found that the closer the small signal ratio of the power tube gate voltage to the LDO input voltage is to 1, the higher the PSRR. Based on this theory, a new structure is added to the traditional LDO, in which a diode connected MOS tube is connected in series with a common source and common gate structure to make the small signal ratio of the gate voltage of the power tube to the input voltage of LDO close to 1. Subsequently, a theoretical analysis of the structure is conducted, and the analysis results show that compared to other PSRR enhancement techniques, LDO with this structure does not have a significant change in PSRR with an increase of load current. The absolute values of PSRR of the LDO before and after improvement are 65 dB and 76 dB respectively, and the improved one’s PSRR is higher in different load currents. Compared to other PSRR enhancement techniques such as bulk driven feedforward and adding a charge pump to isolate the power supply circuit from the LDO main circuit, this method has certain reduction in power consumption and area of the circuit by adding only three MOS tubes to the traditional LDO.

Key words: analog IC, power management, analog LDO, PSRR

中图分类号:

TN432

黄立朝,丁宁,沈泊言,余文中,樊华,曾泳钦,冯全源. 一种高PSRR低压差线性稳压器电路^*[J]. 电子与封装, 2024, 24(4): 040303 .

HUANG Lichao, DING Ning, SHEN Boyan, YU Wenzhong, FAN Hua, ZENG Yongqin, FENG Quanyuan. High PSRR Low Dropout Linear Regulator[J]. Electronics & Packaging, 2024, 24(4): 040303 .

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中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

一种高PSRR低压差线性稳压器电路^*

High PSRR Low Dropout Linear Regulator

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